[PATCH] D64760: [x86] use more phadd for reductions

Sanjay Patel via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jul 16 07:23:53 PDT 2019


spatel updated this revision to Diff 210093.
spatel added a comment.

Patch updated:
Allow 256-bit reductions by extracting and using 1 more 128-bit hop.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D64760/new/

https://reviews.llvm.org/D64760

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/phaddsub-extract.ll
  llvm/test/CodeGen/X86/vector-reduce-add-widen.ll
  llvm/test/CodeGen/X86/vector-reduce-add.ll

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