[llvm] r366179 - [RISCV] Match GNU tools canonical JALR and add aliases
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 15 21:56:43 PDT 2019
Author: asb
Date: Mon Jul 15 21:56:43 2019
New Revision: 366179
URL: http://llvm.org/viewvc/llvm-project?rev=366179&view=rev
Log:
[RISCV] Match GNU tools canonical JALR and add aliases
The canonical GNU form of JALR resembles a load/store instruction rather
than placing the immediate offset as a separate argument, so match this
behaviour. Also add parser-only aliases for the three-operand form, and
add other shorter aliases also emitted by GNU tools.
Differential Revision: https://reviews.llvm.org/D55277
Patch by James Clarke.
Modified:
llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
llvm/trunk/test/CodeGen/RISCV/branch-relaxation.ll
llvm/trunk/test/CodeGen/RISCV/indirectbr.ll
llvm/trunk/test/CodeGen/RISCV/option-rvc.ll
llvm/trunk/test/MC/RISCV/compress-rv32i.s
llvm/trunk/test/MC/RISCV/fixups.s
llvm/trunk/test/MC/RISCV/rv32e-valid.s
llvm/trunk/test/MC/RISCV/rv32i-valid.s
llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td?rev=366179&r1=366178&r2=366179&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td Mon Jul 15 21:56:43 2019
@@ -357,7 +357,7 @@ def JAL : RVInstJ<OPC_JAL, (outs GPR:$rd
let isCall = 1 in
def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd),
(ins GPR:$rs1, simm12:$imm12),
- "jalr", "$rd, $rs1, $imm12">;
+ "jalr", "$rd, ${imm12}(${rs1})">;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
def BEQ : BranchCC_rri<0b000, "beq">;
@@ -597,12 +597,23 @@ def : InstAlias<"bgtu $rs, $rt, $offset"
def : InstAlias<"bleu $rs, $rt, $offset",
(BGEU GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
-// "ret" has more weight since "ret" and "jr" alias the same "jalr" instruction.
-def : InstAlias<"j $offset", (JAL X0, simm21_lsb0_jal:$offset)>;
-def : InstAlias<"jal $offset", (JAL X1, simm21_lsb0_jal:$offset)>;
-def : InstAlias<"jr $rs", (JALR X0, GPR:$rs, 0)>;
-def : InstAlias<"jalr $rs", (JALR X1, GPR:$rs, 0)>;
-def : InstAlias<"ret", (JALR X0, X1, 0), 2>;
+def : InstAlias<"j $offset", (JAL X0, simm21_lsb0_jal:$offset)>;
+def : InstAlias<"jal $offset", (JAL X1, simm21_lsb0_jal:$offset)>;
+
+// Non-zero offset aliases of "jalr" are the lowest weight, followed by the
+// two-register form, then the one-register forms and finally "ret".
+def : InstAlias<"jr $rs", (JALR X0, GPR:$rs, 0), 3>;
+def : InstAlias<"jr ${offset}(${rs})", (JALR X0, GPR:$rs, simm12:$offset)>;
+def : InstAlias<"jalr $rs", (JALR X1, GPR:$rs, 0), 3>;
+def : InstAlias<"jalr ${offset}(${rs})", (JALR X1, GPR:$rs, simm12:$offset)>;
+def : InstAlias<"jalr $rd, $rs", (JALR GPR:$rd, GPR:$rs, 0), 2>;
+def : InstAlias<"ret", (JALR X0, X1, 0), 4>;
+
+// Non-canonical forms for jump targets also accepted by the assembler.
+def : InstAlias<"jr $rs, $offset", (JALR X0, GPR:$rs, simm12:$offset), 0>;
+def : InstAlias<"jalr $rs, $offset", (JALR X1, GPR:$rs, simm12:$offset), 0>;
+def : InstAlias<"jalr $rd, $rs, $offset", (JALR GPR:$rd, GPR:$rs, simm12:$offset), 0>;
+
// TODO call
// TODO tail
Modified: llvm/trunk/test/CodeGen/RISCV/branch-relaxation.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/branch-relaxation.ll?rev=366179&r1=366178&r2=366179&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/branch-relaxation.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/branch-relaxation.ll Mon Jul 15 21:56:43 2019
@@ -25,6 +25,7 @@ tail:
ret void
}
+; TODO: Extend simm12's MCOperandPredicate so the jalr zero is printed as a jr.
define i32 @relax_jal(i1 %a) nounwind {
; CHECK-LABEL: relax_jal:
; CHECK: # %bb.0:
@@ -32,7 +33,7 @@ define i32 @relax_jal(i1 %a) nounwind {
; CHECK-NEXT: bnez a0, .LBB1_1
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: lui a0, %hi(.LBB1_2)
-; CHECK-NEXT: jalr zero, a0, %lo(.LBB1_2)
+; CHECK-NEXT: jalr zero, %lo(.LBB1_2)(a0)
; CHECK-NEXT: .LBB1_1: # %iftrue
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
Modified: llvm/trunk/test/CodeGen/RISCV/indirectbr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/indirectbr.ll?rev=366179&r1=366178&r2=366179&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/indirectbr.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/indirectbr.ll Mon Jul 15 21:56:43 2019
@@ -25,7 +25,7 @@ define i32 @indirectbr_with_offset(i8* %
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: jalr zero, a0, 1380
+; RV32I-NEXT: jr 1380(a0)
; RV32I-NEXT: .LBB1_1:
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: lw ra, 12(sp)
Modified: llvm/trunk/test/CodeGen/RISCV/option-rvc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/option-rvc.ll?rev=366179&r1=366178&r2=366179&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/option-rvc.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/option-rvc.ll Mon Jul 15 21:56:43 2019
@@ -8,7 +8,7 @@
define i32 @add(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: add:
; CHECK: add a0, a1, a0
-; CHECK-NEXT: jalr zero, ra, 0
+; CHECK-NEXT: jalr zero, 0(ra)
tail call void asm sideeffect ".option rvc", ""()
%add = add nsw i32 %b, %a
ret i32 %add
Modified: llvm/trunk/test/MC/RISCV/compress-rv32i.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/compress-rv32i.s?rev=366179&r1=366178&r2=366179&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/compress-rv32i.s (original)
+++ llvm/trunk/test/MC/RISCV/compress-rv32i.s Mon Jul 15 21:56:43 2019
@@ -168,7 +168,7 @@ lw ra, 252(sp)
# CHECK-ALIAS: ret
# CHECK-INST: c.jr ra
# CHECK: # encoding: [0x82,0x80]
-jalr zero, ra, 0
+jalr zero, 0(ra)
# CHECK-BYTES: 92 80
# CHECK-ALIAS: add ra, zero, tp
@@ -192,7 +192,7 @@ ebreak
# CHECK-ALIAS: jalr s0
# CHECK-INST: c.jalr s0
# CHECK: # encoding: [0x02,0x94]
-jalr ra, s0, 0
+jalr ra, 0(s0)
# CHECK-BYTES: 3e 94
# CHECK-ALIAS: add s0, s0, a5
Modified: llvm/trunk/test/MC/RISCV/fixups.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/fixups.s?rev=366179&r1=366178&r2=366179&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/fixups.s (original)
+++ llvm/trunk/test/MC/RISCV/fixups.s Mon Jul 15 21:56:43 2019
@@ -68,16 +68,16 @@ func:
call func
# CHECK-FIXUP: fixup A - offset: 0, value: func, kind: fixup_riscv_call
# CHECK-INSTR: auipc ra, 0
-# CHECK-INSTR: jalr ra, ra, -100
+# CHECK-INSTR: jalr ra, -100(ra)
.fill 10000
call func
# CHECK-FIXUP: fixup A - offset: 0, value: func, kind: fixup_riscv_call
# CHECK-INSTR: auipc ra, 1048574
-# CHECK-INSTR: jalr ra, ra, -1916
+# CHECK-INSTR: jalr ra, -1916(ra)
.fill 20888
call func
# CHECK-FIXUP: fixup A - offset: 0, value: func, kind: fixup_riscv_call
# CHECK-INSTR: auipc ra, 1048568
-# CHECK-INSTR: jalr ra, ra, 1764
+# CHECK-INSTR: jalr ra, 1764(ra)
Modified: llvm/trunk/test/MC/RISCV/rv32e-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rv32e-valid.s?rev=366179&r1=366178&r2=366179&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rv32e-valid.s (original)
+++ llvm/trunk/test/MC/RISCV/rv32e-valid.s Mon Jul 15 21:56:43 2019
@@ -14,7 +14,7 @@ auipc x1, 2
# CHECK-ASM-AND-OBJ: jal sp, 4
jal x2, 4
-# CHECK-ASM-AND-OBJ: jalr gp, gp, 4
+# CHECK-ASM-AND-OBJ: jalr gp, 4(gp)
jalr x3, x3, 4
# CHECK-ASM-AND-OBJ: beq tp, t0, 8
Modified: llvm/trunk/test/MC/RISCV/rv32i-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rv32i-valid.s?rev=366179&r1=366178&r2=366179&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rv32i-valid.s (original)
+++ llvm/trunk/test/MC/RISCV/rv32i-valid.s Mon Jul 15 21:56:43 2019
@@ -94,27 +94,21 @@ jal s0, (0xff-99)
# CHECK-OBJ: jal zero, 0
jal zero, .
-# CHECK-ASM-AND-OBJ: jalr a0, a1, -2048
+# CHECK-ASM-AND-OBJ: jalr a0, -2048(a1)
# CHECK-ASM: encoding: [0x67,0x85,0x05,0x80]
-jalr a0, a1, -2048
-# CHECK-ASM-AND-OBJ: jalr a0, a1, -2048
+jalr a0, -2048(a1)
+# CHECK-ASM-AND-OBJ: jalr a0, -2048(a1)
# CHECK-ASM: encoding: [0x67,0x85,0x05,0x80]
-jalr a0, a1, ~2047
-# CHECK-ASM-AND-OBJ: jalr a0, a1, 0
-# CHECK-ASM: encoding: [0x67,0x85,0x05,0x00]
-jalr a0, a1, !1
-# CHECK-ASM-AND-OBJ: jalr a0, a1, -2048
-# CHECK-ASM: encoding: [0x67,0x85,0x05,0x80]
-jalr a0, a1, %lo(2048)
-# CHECK-ASM-AND-OBJ: jalr t2, t1, 2047
+jalr a0, %lo(2048)(a1)
+# CHECK-ASM-AND-OBJ: jalr t2, 2047(t1)
# CHECK-ASM: encoding: [0xe7,0x03,0xf3,0x7f]
-jalr t2, t1, 2047
-# CHECK-ASM-AND-OBJ: jalr sp, zero, 256
+jalr t2, 2047(t1)
+# CHECK-ASM-AND-OBJ: jalr sp, 256(zero)
# CHECK-ASM: encoding: [0x67,0x01,0x00,0x10]
jalr sp, zero, 256
-# CHECK-ASM-AND-OBJ: jalr a1, a2, 30
+# CHECK-ASM-AND-OBJ: jalr a1, 30(a2)
# CHECK-ASM: encoding: [0xe7,0x05,0xe6,0x01]
-jalr a1, a2, CONST
+jalr a1, CONST(a2)
# CHECK-ASM-AND-OBJ: beq s1, s1, 102
# CHECK-ASM: encoding: [0x63,0x83,0x94,0x06]
Modified: llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s?rev=366179&r1=366178&r2=366179&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s (original)
+++ llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s Mon Jul 15 21:56:43 2019
@@ -139,13 +139,31 @@ jal foo
# CHECK-OBJ: jal 0
# CHECK-OBJ: R_RISCV_JAL a0
jal a0
-# CHECK-S-OBJ-NOALIAS: jalr zero, s4, 0
+# CHECK-S-OBJ-NOALIAS: jalr zero, 0(s4)
# CHECK-S-OBJ: jr s4
jr x20
-# CHECK-S-OBJ-NOALIAS: jalr ra, s5, 0
-# CHECK-S-OBJ: jalr s5
-jalr x21
-# CHECK-S-OBJ-NOALIAS: jalr zero, ra, 0
+# CHECK-S-OBJ-NOALIAS: jalr zero, 6(s5)
+# CHECK-S-OBJ: jr 6(s5)
+jr 6(x21)
+# CHECK-S-OBJ-NOALIAS: jalr zero, 7(s6)
+# CHECK-S-OBJ: jr 7(s6)
+jr x22, 7
+# CHECK-S-OBJ-NOALIAS: jalr ra, 0(s4)
+# CHECK-S-OBJ: jalr s4
+jalr x20
+# CHECK-S-OBJ-NOALIAS: jalr ra, 8(s5)
+# CHECK-S-OBJ: jalr 8(s5)
+jalr 8(x21)
+# CHECK-S-OBJ-NOALIAS: jalr s6, 0(s7)
+# CHECK-S-OBJ: jalr s6, s7
+jalr x22, x23
+# CHECK-S-OBJ-NOALIAS: jalr ra, 9(s8)
+# CHECK-S-OBJ: jalr 9(s8)
+jalr x24, 9
+# CHECK-S-OBJ-NOALIAS: jalr s9, 11(s10)
+# CHECK-S-OBJ: jalr s9, 11(s10)
+jalr x25, x26, 11
+# CHECK-S-OBJ-NOALIAS: jalr zero, 0(ra)
# CHECK-S-OBJ: ret
ret
# TODO call
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