[PATCH] D64766: [AMDGPU] Enable merging m0 initializations.

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp:458-459
+getFirstNonProlog(MachineBasicBlock *MBB, const TargetInstrInfo *TII) {
+  MachineBasicBlock::iterator I = MBB->getFirstNonPHI();
+  while (I != MBB->end() && TII->isBasicBlockPrologue(*I))
+    ++I;
----------------
arsenm wrote:
> rampitec wrote:
> > arsenm wrote:
> > > Why does this need to care about the prolog instructions? (FYI I'm planning on eliminating the rarely followed concept)
> > You actually cannot, it was created to prevent RA from insrting spills into endif/else block before we updated exec mask.
> Yes, I'm working on splitting the blocks to avoid this
I never found a way to properly split a block for that. Assume you split it and endif sequence is in the 1st block. What would prevent RA from inserting spill/restore there? You will need to mark a whole block as not suitable for spills and in addition prohibit RA from inserting any COPY instructions there.

Besides until there is another way m0 init must follow prologue anyway. If it is inserted before endif sequence that will break a contiguous sequence of prologue instructions and we will have bogus spilling again.


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  https://reviews.llvm.org/D64766/new/

https://reviews.llvm.org/D64766