[llvm] r366118 - AMDGPU/GlobalISel: Fix not constraining result reg of copies to VCC
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 15 12:45:50 PDT 2019
Author: arsenm
Date: Mon Jul 15 12:45:49 2019
New Revision: 366118
URL: http://llvm.org/viewvc/llvm-project?rev=366118&view=rev
Log:
AMDGPU/GlobalISel: Fix not constraining result reg of copies to VCC
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp?rev=366118&r1=366117&r2=366118&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp Mon Jul 15 12:45:49 2019
@@ -116,6 +116,10 @@ bool AMDGPUInstructionSelector::selectCO
return RBI.constrainGenericRegister(DstReg, *RC, MRI);
}
+ // TODO: Should probably leave the copy and let copyPhysReg expand it.
+ if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), MRI))
+ return false;
+
BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), DstReg)
.addImm(0)
.addReg(SrcReg);
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir?rev=366118&r1=366117&r2=366118&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir Mon Jul 15 12:45:49 2019
@@ -242,3 +242,29 @@ body: |
bb.1:
...
+
+---
+
+name: copy_sgpr_s1_to_vcc_constrain
+legalized: true
+regBankSelected: true
+
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+ ; WAVE64-LABEL: name: copy_sgpr_s1_to_vcc_constrain
+ ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NE_U32_e64_]]
+ ; WAVE32-LABEL: name: copy_sgpr_s1_to_vcc_constrain
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NE_U32_e64_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:sgpr(s1) = G_TRUNC %0
+ %2:vcc(s1) = COPY %1
+ S_ENDPGM 0, implicit %2
+
+...
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