[llvm] r366114 - AMDGPU/GlobalISel: Fix G_ICMP for wave32

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Mon Jul 15 12:39:31 2019
New Revision: 366114

URL: http://llvm.org/viewvc/llvm-project?rev=366114&view=rev
Log:
AMDGPU/GlobalISel: Fix G_ICMP for wave32

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp?rev=366114&r1=366113&r2=366114&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp Mon Jul 15 12:39:31 2019
@@ -583,7 +583,7 @@ bool AMDGPUInstructionSelector::selectG_
   MachineBasicBlock *BB = I.getParent();
   MachineFunction *MF = BB->getParent();
   MachineRegisterInfo &MRI = MF->getRegInfo();
-  DebugLoc DL = I.getDebugLoc();
+  const DebugLoc &DL = I.getDebugLoc();
 
   unsigned SrcReg = I.getOperand(2).getReg();
   unsigned Size = RBI.getSizeInBits(SrcReg, MRI, TRI);
@@ -616,7 +616,7 @@ bool AMDGPUInstructionSelector::selectG_
             .add(I.getOperand(2))
             .add(I.getOperand(3));
   RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(),
-                               AMDGPU::SReg_64RegClass, MRI);
+                               *TRI.getBoolRC(), MRI);
   bool Ret = constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI);
   I.eraseFromParent();
   return Ret;

Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir?rev=366114&r1=366113&r2=366114&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir Mon Jul 15 12:39:31 2019
@@ -1,5 +1,6 @@
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN -DVCCRC=sreg_64_xexec %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN -DVCCRC=sreg_64_xexec %s
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN -DVCCRC=sreg_32_xm0_xexec %s
 
 ---
 name:            icmp_s32_s_mix
@@ -129,8 +130,8 @@ regBankSelected: true
 # GCN: [[VGPR7:%[0-9]+]]:vgpr_32 = COPY $vgpr7
 # GCN: [[VGPR8:%[0-9]+]]:vgpr_32 = COPY $vgpr8
 # GCN: [[VGPR9:%[0-9]+]]:vgpr_32 = COPY $vgpr9
-# GCN: [[COND0:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 [[VGPR2]], [[VGPR3]]
-# GCN: [[COND1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 [[VGPR6]], [[VGPR7]]
+# GCN: [[COND0:%[0-9]+]]:[[VCCRC]] = V_CMP_NE_U32_e64 [[VGPR2]], [[VGPR3]]
+# GCN: [[COND1:%[0-9]+]]:[[VCCRC]] = V_CMP_NE_U32_e64 [[VGPR6]], [[VGPR7]]
 # GCN: V_CNDMASK_B32_e64 0, [[VGPR9]], 0, [[VGPR8]], [[COND0]]
 # GCN: V_CNDMASK_B32_e64 0, [[VGPR5]], 0, [[VGPR4]], [[COND1]]
 
@@ -339,8 +340,8 @@ legalized:       true
 regBankSelected: true
 
 # GCN-LABEL: name: icmp_eq_ne_p3_vv
-# GCN: %2:sreg_64_xexec = V_CMP_EQ_U32_e64 %0, %1, implicit $exec
-# GCN: %3:sreg_64_xexec = V_CMP_NE_U32_e64 %0, %1, implicit $exec
+# GCN: %2:[[VCCRC]] = V_CMP_EQ_U32_e64 %0, %1, implicit $exec
+# GCN: %3:[[VCCRC]] = V_CMP_NE_U32_e64 %0, %1, implicit $exec
 
 body: |
   bb.0: