[PATCH] D64760: [x86] use more phadd for reductions

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:35618
+  if ((((VecVT == MVT::v8i16 || VecVT == MVT::v4i32) && Subtarget.hasSSSE3()) ||
+       ((VecVT == MVT::v4f32 || VecVT == MVT::v2f64) && Subtarget.hasSSE3()))) {
+    // TODO: Allow FADD with reduction and/or reassociation and no-signed-zeros.
----------------
(style) early-out if this is not the case


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D64760/new/

https://reviews.llvm.org/D64760