[PATCH] D64751: [RISCV] Add support for lowering floating point inlineasm clobbers

[Simon Cook via Phabricator via llvm-commits]

simoncook created this revision.
simoncook added reviewers: asb, edward-jones, lewis-revill.
Herald added subscribers: llvm-commits, lenary, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, johnrusso, rbar, hiraditya.
Herald added a project: LLVM.

This adds the required extension to RISC-V's getRegForInlineAsmConstraint
in order to be able to correctly distringuish between the 32 and 64-bit
floating point registers when the generic fX name appears in inlineasm
clobber contraints. It also adds a check to validate that callee saved
floating point registers are only saved in this case when a hard-float
ABI is selected.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D64751

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/inline-asm-clobbers.ll

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