[PATCH] D64726: AMDGPU/GlobalISel: Fix not constraining result reg of copies to VCC

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: tstellar, nhaehnle.
Herald added subscribers: Petar.Avramovic, t-tye, tpr, dstuttard, rovka, yaxunl, wdng, jvesely, kzhuravl.

https://reviews.llvm.org/D64726

Files:
  lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir


Index: test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
===================================================================
--- test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
+++ test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
@@ -242,3 +242,29 @@
   bb.1:
 
 ...
+
+---
+
+name:            copy_sgpr_s1_to_vcc_constrain
+legalized:       true
+regBankSelected: true
+
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+    ; WAVE64-LABEL: name: copy_sgpr_s1_to_vcc_constrain
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
+    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NE_U32_e64_]]
+    ; WAVE32-LABEL: name: copy_sgpr_s1_to_vcc_constrain
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
+    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NE_U32_e64_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s1) = G_TRUNC %0
+    %2:vcc(s1) = COPY %1
+    S_ENDPGM 0, implicit %2
+
+...
Index: lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -116,6 +116,10 @@
       return RBI.constrainGenericRegister(DstReg, *RC, MRI);
     }
 
+    // TODO: Should probably leave the copy and let copyPhysReg expand it.
+    if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), MRI))
+      return false;
+
     BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), DstReg)
       .addImm(0)
       .addReg(SrcReg);


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