[PATCH] D64709: [AMDGPU] fixed scheduler crash in gfx908

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec updated this revision to Diff 209754.
rampitec edited the summary of this revision.
rampitec added a comment.

Added test.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D64709/new/

https://reviews.llvm.org/D64709

Files:
  lib/Target/AMDGPU/AMDGPUSubtarget.cpp
  test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir


Index: test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir
@@ -0,0 +1,22 @@
+# RUN: llc -march=amdgcn -mcpu=gfx908 %s -run-pass=post-RA-sched -o - | FileCheck -check-prefix=GCN %s
+
+# GCN-LABEL: name: test
+# GCN: V_MFMA_F32_32X32X1F32
+# GCN: S_BARRIER
+# GCN: S_NOP 0
+# GCN: V_ACCVGPR_READ_B32
+# GCN: BUFFER_STORE_DWORD_OFFEN
+---
+name:            test
+body:             |
+  bb.0.entry:
+
+    $sgpr6 = S_MOV_B32 $sgpr5
+    $sgpr10_sgpr11 = S_MOV_B64 $sgpr2_sgpr3, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11, implicit $sgpr0_sgpr1_sgpr2_sgpr3
+    $sgpr8_sgpr9 = S_MOV_B64 $sgpr0_sgpr1, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3
+    S_BARRIER
+    $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = V_MFMA_F32_32X32X1F32 undef $vgpr0, undef $vgpr0, 0, 0, 0, 2, implicit $exec
+    $vgpr0 = V_ACCVGPR_READ_B32 $agpr31, implicit $exec
+    BUFFER_STORE_DWORD_OFFEN killed $vgpr0, undef $vgpr0, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr6, 0, 0, 0, 0, 0, implicit $exec
+
+...
Index: lib/Target/AMDGPU/AMDGPUSubtarget.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+++ lib/Target/AMDGPU/AMDGPUSubtarget.cpp
@@ -765,8 +765,8 @@
   FillMFMAShadowMutation(const SIInstrInfo *tii) : TII(tii) {}
 
   bool isSALU(const SUnit *SU) const {
-    const MachineInstr &MI = *SU->getInstr();
-    return TII->isSALU(MI) && !MI.isTerminator();
+    const MachineInstr *MI = SU->getInstr();
+    return MI && TII->isSALU(*MI) && !MI->isTerminator();
   }
 
   bool canAddEdge(const SUnit *Succ, const SUnit *Pred) const {


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