[PATCH] D64699: [X86] Use getLimitedValue to clamp and out of range shift amount instead of asserting.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.

I think we only turn out of range shiftss to undef when
all elements are out of range or the shift amount is a splat out
of range. I'm not sure which, I didn't check.

During lowering we can split a shift where some elements
are out of range into multiple shifts. This can create a
new shift with a splat shift amount that is out of range.

This patch clamps the shift amount to be in range using
getLimitedValue. I went with that because it was simple.
Alternatively we could return undef or all 0s or something.
Or modulo the shift amount. I'm open to whatever.

Fixes PR42615.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D64699

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/pr42615.ll


Index: llvm/test/CodeGen/X86/pr42615.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/pr42615.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-w64-windows-gnu -mattr=sse2 | FileCheck %s
+
+define <2 x i64> @_ZL14c_v256_ziphi_86c_v256S_() {
+; CHECK-LABEL: _ZL14c_v256_ziphi_86c_v256S_:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,0]
+; CHECK-NEXT:    movdqa %xmm0, %xmm1
+; CHECK-NEXT:    psllq $56, %xmm1
+; CHECK-NEXT:    psllq $63, %xmm0
+; CHECK-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
+; CHECK-NEXT:    retl
+entry:
+  %a.sroa.0.sroa.1.0.copyload = load i64, i64* undef, align 4
+  %0 = insertelement <2 x i64> undef, i64 %a.sroa.0.sroa.1.0.copyload, i32 1
+  %1 = shl <2 x i64> %0, <i64 56, i64 -72057594037927936>
+  %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> <i32 0, i32 3>
+  ret <2 x i64> %2
+}
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -25022,9 +25022,8 @@
   APInt APIntShiftAmt;
   if (!isConstantSplat(Amt, APIntShiftAmt))
     return SDValue();
-  assert(APIntShiftAmt.ult(VT.getScalarSizeInBits()) &&
-         "Out of range shift amount");
-  uint64_t ShiftAmt = APIntShiftAmt.getZExtValue();
+  uint64_t ShiftAmt =
+      APIntShiftAmt.getLimitedValue(VT.getScalarSizeInBits() - 1);
 
   if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
     return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);


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