[PATCH] D64596: [AMDGPU] Skip calculating callee saved registers for entry function.

[Michael Liao via Phabricator via llvm-commits]

hliao added a comment.

In D64596#1581524 <https://reviews.llvm.org/D64596#1581524>, @arsenm wrote:

> What is this supposed to solve?


the issue happens when we need to spill FP when all SGRPs used.  However, register scavenger is only allocated when necessary for entry function. The newly created frame object when we determine whether FP needs to be spilled breaks later process as RS is not allocated at the beginning.


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