[PATCH] D64551: [X86] EltsFromConsecutiveLoads - support common source loads

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

In D64551#1580222 <https://reviews.llvm.org/D64551#1580222>, @RKSimon wrote:

> In D64551#1580187 <https://reviews.llvm.org/D64551#1580187>, @lebedev.ri wrote:
>
> > Does this need to do anything to ensure that there are no interferences, in the sense of non-known-noalias writes?
>
>
> That's what areNonVolatileConsecutiveLoads handles no?


It isn't fully obvious whether that only checks that the loads are from sequential locations in memory,
or whether it also checks that it is *legal* to perform those loads as one, at least to me.
I.e. i'm expecting this doesn't fold:

  define <4 x float> @load_float4_float3_as_float2_float__with_write(<4 x float>* nocapture readonly dereferenceable(16)) {
    %2 = bitcast <4 x float>* %0 to <2 x float>*
    %3 = load <2 x float>, <2 x float>* %2, align 4
    %4 = extractelement <2 x float> %3, i32 0
    %5 = insertelement <4 x float> undef, float %4, i32 0
    %6 = extractelement <2 x float> %3, i32 1
    %7 = insertelement <4 x float> %5, float %6, i32 1
    %8 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 2
    store float 42.0, float* %8 ; !!!
    %9 = load float, float* %8, align 4
    %10 = insertelement <4 x float> %7, float %9, i32 2
    ret <4 x float> %10
  }

Is that what `if (LD->getChain() != Base->getChain()) return false;` does?


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