[llvm] r365704 - [X86] Add a few more TBM and BLSI test cases that show the same issue that r352306 fixed for BLSR.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 10 15:44:25 PDT 2019
Author: ctopper
Date: Wed Jul 10 15:44:24 2019
New Revision: 365704
URL: http://llvm.org/viewvc/llvm-project?rev=365704&view=rev
Log:
[X86] Add a few more TBM and BLSI test cases that show the same issue that r352306 fixed for BLSR.
Modified:
llvm/trunk/test/CodeGen/X86/bmi.ll
llvm/trunk/test/CodeGen/X86/tbm_patterns.ll
Modified: llvm/trunk/test/CodeGen/X86/bmi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi.ll?rev=365704&r1=365703&r2=365704&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bmi.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bmi.ll Wed Jul 10 15:44:24 2019
@@ -1148,25 +1148,127 @@ define i64 @blsr64_branch(i64 %x) {
ret i64 %tmp2
}
+define i32 @blsi32_branch(i32 %x) {
+; X86-LABEL: blsi32_branch:
+; X86: # %bb.0:
+; X86-NEXT: pushl %esi
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .cfi_offset %esi, -8
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl %eax, %esi
+; X86-NEXT: negl %esi
+; X86-NEXT: andl %eax, %esi
+; X86-NEXT: jne .LBB48_2
+; X86-NEXT: # %bb.1:
+; X86-NEXT: calll bar
+; X86-NEXT: .LBB48_2:
+; X86-NEXT: movl %esi, %eax
+; X86-NEXT: popl %esi
+; X86-NEXT: .cfi_def_cfa_offset 4
+; X86-NEXT: retl
+;
+; X64-LABEL: blsi32_branch:
+; X64: # %bb.0:
+; X64-NEXT: pushq %rbx
+; X64-NEXT: .cfi_def_cfa_offset 16
+; X64-NEXT: .cfi_offset %rbx, -16
+; X64-NEXT: movl %edi, %ebx
+; X64-NEXT: negl %ebx
+; X64-NEXT: andl %edi, %ebx
+; X64-NEXT: jne .LBB48_2
+; X64-NEXT: # %bb.1:
+; X64-NEXT: callq bar
+; X64-NEXT: .LBB48_2:
+; X64-NEXT: movl %ebx, %eax
+; X64-NEXT: popq %rbx
+; X64-NEXT: .cfi_def_cfa_offset 8
+; X64-NEXT: retq
+ %tmp = sub i32 0, %x
+ %tmp2 = and i32 %x, %tmp
+ %cmp = icmp eq i32 %tmp2, 0
+ br i1 %cmp, label %1, label %2
+
+ tail call void @bar()
+ br label %2
+ ret i32 %tmp2
+}
+
+define i64 @blsi64_branch(i64 %x) {
+; X86-LABEL: blsi64_branch:
+; X86: # %bb.0:
+; X86-NEXT: pushl %edi
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: pushl %esi
+; X86-NEXT: .cfi_def_cfa_offset 12
+; X86-NEXT: .cfi_offset %esi, -12
+; X86-NEXT: .cfi_offset %edi, -8
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: xorl %esi, %esi
+; X86-NEXT: movl %eax, %edi
+; X86-NEXT: negl %edi
+; X86-NEXT: sbbl %ecx, %esi
+; X86-NEXT: andl %ecx, %esi
+; X86-NEXT: andl %eax, %edi
+; X86-NEXT: movl %edi, %eax
+; X86-NEXT: orl %esi, %eax
+; X86-NEXT: jne .LBB49_2
+; X86-NEXT: # %bb.1:
+; X86-NEXT: calll bar
+; X86-NEXT: .LBB49_2:
+; X86-NEXT: movl %edi, %eax
+; X86-NEXT: movl %esi, %edx
+; X86-NEXT: popl %esi
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: popl %edi
+; X86-NEXT: .cfi_def_cfa_offset 4
+; X86-NEXT: retl
+;
+; X64-LABEL: blsi64_branch:
+; X64: # %bb.0:
+; X64-NEXT: pushq %rbx
+; X64-NEXT: .cfi_def_cfa_offset 16
+; X64-NEXT: .cfi_offset %rbx, -16
+; X64-NEXT: movq %rdi, %rbx
+; X64-NEXT: negq %rbx
+; X64-NEXT: andq %rdi, %rbx
+; X64-NEXT: jne .LBB49_2
+; X64-NEXT: # %bb.1:
+; X64-NEXT: callq bar
+; X64-NEXT: .LBB49_2:
+; X64-NEXT: movq %rbx, %rax
+; X64-NEXT: popq %rbx
+; X64-NEXT: .cfi_def_cfa_offset 8
+; X64-NEXT: retq
+ %tmp = sub i64 0, %x
+ %tmp2 = and i64 %x, %tmp
+ %cmp = icmp eq i64 %tmp2, 0
+ br i1 %cmp, label %1, label %2
+
+ tail call void @bar()
+ br label %2
+ ret i64 %tmp2
+}
+
declare void @bar()
define void @pr42118_i32(i32 %x) {
; X86-LABEL: pr42118_i32:
; X86: # %bb.0:
; X86-NEXT: blsrl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: jne .LBB48_1
+; X86-NEXT: jne .LBB50_1
; X86-NEXT: # %bb.2:
; X86-NEXT: jmp bar # TAILCALL
-; X86-NEXT: .LBB48_1:
+; X86-NEXT: .LBB50_1:
; X86-NEXT: retl
;
; X64-LABEL: pr42118_i32:
; X64: # %bb.0:
; X64-NEXT: blsrl %edi, %eax
-; X64-NEXT: jne .LBB48_1
+; X64-NEXT: jne .LBB50_1
; X64-NEXT: # %bb.2:
; X64-NEXT: jmp bar # TAILCALL
-; X64-NEXT: .LBB48_1:
+; X64-NEXT: .LBB50_1:
; X64-NEXT: retq
%tmp = sub i32 0, %x
%tmp1 = and i32 %tmp, %x
@@ -1194,12 +1296,12 @@ define void @pr42118_i64(i64 %x) {
; X86-NEXT: andl %eax, %edx
; X86-NEXT: andl %ecx, %esi
; X86-NEXT: orl %edx, %esi
-; X86-NEXT: jne .LBB49_1
+; X86-NEXT: jne .LBB51_1
; X86-NEXT: # %bb.2:
; X86-NEXT: popl %esi
; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: jmp bar # TAILCALL
-; X86-NEXT: .LBB49_1:
+; X86-NEXT: .LBB51_1:
; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: popl %esi
; X86-NEXT: .cfi_def_cfa_offset 4
@@ -1208,10 +1310,10 @@ define void @pr42118_i64(i64 %x) {
; X64-LABEL: pr42118_i64:
; X64: # %bb.0:
; X64-NEXT: blsrq %rdi, %rax
-; X64-NEXT: jne .LBB49_1
+; X64-NEXT: jne .LBB51_1
; X64-NEXT: # %bb.2:
; X64-NEXT: jmp bar # TAILCALL
-; X64-NEXT: .LBB49_1:
+; X64-NEXT: .LBB51_1:
; X64-NEXT: retq
%tmp = sub i64 0, %x
%tmp1 = and i64 %tmp, %x
@@ -1229,11 +1331,11 @@ define i32 @blsi_cflag_32(i32 %x, i32 %y
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: testl %eax, %eax
-; X86-NEXT: jne .LBB50_1
+; X86-NEXT: jne .LBB52_1
; X86-NEXT: # %bb.2:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: retl
-; X86-NEXT: .LBB50_1:
+; X86-NEXT: .LBB52_1:
; X86-NEXT: blsil %eax, %eax
; X86-NEXT: retl
;
@@ -1262,15 +1364,15 @@ define i64 @blsi_cflag_64(i64 %x, i64 %y
; X86-NEXT: sbbl %esi, %edx
; X86-NEXT: movl %ecx, %edi
; X86-NEXT: orl %esi, %edi
-; X86-NEXT: jne .LBB51_1
+; X86-NEXT: jne .LBB53_1
; X86-NEXT: # %bb.2:
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: jmp .LBB51_3
-; X86-NEXT: .LBB51_1:
+; X86-NEXT: jmp .LBB53_3
+; X86-NEXT: .LBB53_1:
; X86-NEXT: andl %esi, %edx
; X86-NEXT: andl %ecx, %eax
-; X86-NEXT: .LBB51_3:
+; X86-NEXT: .LBB53_3:
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: retl
Modified: llvm/trunk/test/CodeGen/X86/tbm_patterns.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tbm_patterns.ll?rev=365704&r1=365703&r2=365704&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tbm_patterns.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tbm_patterns.ll Wed Jul 10 15:44:24 2019
@@ -1,8 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+tbm < %s | FileCheck %s
-; TODO - Patterns fail to fold with ZF flags and prevents TBM instruction selection.
-
define i32 @test_x86_tbm_bextri_u32(i32 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_bextri_u32:
; CHECK: # %bb.0:
@@ -873,3 +871,113 @@ define i64 @masked_blcic(i64) {
%5 = and i64 %4, %3
ret i64 %5
}
+
+define i32 @blcic32_branch(i32 %x) nounwind {
+; CHECK-LABEL: blcic32_branch:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: movl %edi, %ebx
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: notl %eax
+; CHECK-NEXT: incl %ebx
+; CHECK-NEXT: andl %eax, %ebx
+; CHECK-NEXT: jne .LBB69_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: callq bar
+; CHECK-NEXT: .LBB69_2:
+; CHECK-NEXT: movl %ebx, %eax
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: retq
+ %tmp = xor i32 %x, -1
+ %tmp2 = add i32 %x, 1
+ %tmp3 = and i32 %tmp, %tmp2
+ %cmp = icmp eq i32 %tmp3, 0
+ br i1 %cmp, label %1, label %2
+
+ tail call void @bar()
+ br label %2
+ ret i32 %tmp3
+}
+
+define i64 @blcic64_branch(i64 %x) nounwind {
+; CHECK-LABEL: blcic64_branch:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: movq %rdi, %rbx
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: notq %rax
+; CHECK-NEXT: incq %rbx
+; CHECK-NEXT: andq %rax, %rbx
+; CHECK-NEXT: jne .LBB70_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: callq bar
+; CHECK-NEXT: .LBB70_2:
+; CHECK-NEXT: movq %rbx, %rax
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: retq
+ %tmp = xor i64 %x, -1
+ %tmp2 = add i64 %x, 1
+ %tmp3 = and i64 %tmp, %tmp2
+ %cmp = icmp eq i64 %tmp3, 0
+ br i1 %cmp, label %1, label %2
+
+ tail call void @bar()
+ br label %2
+ ret i64 %tmp3
+}
+
+define i32 @tzmsk32_branch(i32 %x) nounwind {
+; CHECK-LABEL: tzmsk32_branch:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: movl %edi, %ebx
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: notl %eax
+; CHECK-NEXT: decl %ebx
+; CHECK-NEXT: andl %eax, %ebx
+; CHECK-NEXT: jne .LBB71_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: callq bar
+; CHECK-NEXT: .LBB71_2:
+; CHECK-NEXT: movl %ebx, %eax
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: retq
+ %tmp = xor i32 %x, -1
+ %tmp2 = add i32 %x, -1
+ %tmp3 = and i32 %tmp, %tmp2
+ %cmp = icmp eq i32 %tmp3, 0
+ br i1 %cmp, label %1, label %2
+
+ tail call void @bar()
+ br label %2
+ ret i32 %tmp3
+}
+
+define i64 @tzmsk64_branch(i64 %x) nounwind {
+; CHECK-LABEL: tzmsk64_branch:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: movq %rdi, %rbx
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: notq %rax
+; CHECK-NEXT: decq %rbx
+; CHECK-NEXT: andq %rax, %rbx
+; CHECK-NEXT: jne .LBB72_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: callq bar
+; CHECK-NEXT: .LBB72_2:
+; CHECK-NEXT: movq %rbx, %rax
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: retq
+ %tmp = xor i64 %x, -1
+ %tmp2 = add i64 %x, -1
+ %tmp3 = and i64 %tmp, %tmp2
+ %cmp = icmp eq i64 %tmp3, 0
+ br i1 %cmp, label %1, label %2
+
+ tail call void @bar()
+ br label %2
+ ret i64 %tmp3
+}
+
+declare void @bar()
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