[PATCH] D64511: AMDGPU/GlobalISel: Allow scalar s1 and/or/xor

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: tstellar, nhaehnle.
Herald added subscribers: Petar.Avramovic, t-tye, tpr, dstuttard, rovka, yaxunl, wdng, jvesely, kzhuravl.

If a 1-bit value is in a 32-bit VGPR, the scalar opcodes set SCC to
whether the result is 0. If the inputs are SCC, these can be copied to
 a 32-bit SGPR to produce an SCC result.


https://reviews.llvm.org/D64511

Files:
  lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir

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