[llvm] r365653 - AMDGPU: Serialize mode from MachineFunctionInfo
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 10 09:09:26 PDT 2019
Author: arsenm
Date: Wed Jul 10 09:09:26 2019
New Revision: 365653
URL: http://llvm.org/viewvc/llvm-project?rev=365653&view=rev
Log:
AMDGPU: Serialize mode from MachineFunctionInfo
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h
llvm/trunk/test/CodeGen/AMDGPU/omod-nsz-flag.mir
llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp?rev=365653&r1=365652&r2=365653&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp Wed Jul 10 09:09:26 2019
@@ -1144,5 +1144,8 @@ bool GCNTargetMachine::parseMachineFunct
MFI->ArgInfo.WorkItemIDZ)))
return true;
+ MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
+ MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
+
return false;
}
Modified: llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp?rev=365653&r1=365652&r2=365653&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp Wed Jul 10 09:09:26 2019
@@ -418,7 +418,8 @@ yaml::SIMachineFunctionInfo::SIMachineFu
ScratchWaveOffsetReg(regToString(MFI.getScratchWaveOffsetReg(), TRI)),
FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
- ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)) {}
+ ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)),
+ Mode(MFI.getMode()) {}
void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this);
Modified: llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h?rev=365653&r1=365652&r2=365653&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h Wed Jul 10 09:09:26 2019
@@ -232,6 +232,31 @@ template <> struct MappingTraits<SIArgum
}
};
+// Default to default mode for default calling convention.
+struct SIMode {
+ bool IEEE = true;
+ bool DX10Clamp = true;
+
+ SIMode() = default;
+
+
+ SIMode(const AMDGPU::SIModeRegisterDefaults &Mode) {
+ IEEE = Mode.IEEE;
+ DX10Clamp = Mode.DX10Clamp;
+ }
+
+ bool operator ==(const SIMode Other) const {
+ return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp;
+ }
+};
+
+template <> struct MappingTraits<SIMode> {
+ static void mapping(IO &YamlIO, SIMode &Mode) {
+ YamlIO.mapOptional("ieee", Mode.IEEE, true);
+ YamlIO.mapOptional("dx10-clamp", Mode.DX10Clamp, true);
+ }
+};
+
struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
uint64_t ExplicitKernArgSize = 0;
unsigned MaxKernArgAlign = 0;
@@ -247,6 +272,7 @@ struct SIMachineFunctionInfo final : pub
StringValue StackPtrOffsetReg = "$sp_reg";
Optional<SIArgumentInfo> ArgInfo;
+ SIMode Mode;
SIMachineFunctionInfo() = default;
SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,
@@ -275,6 +301,7 @@ template <> struct MappingTraits<SIMachi
YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
StringValue("$sp_reg"));
YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
+ YamlIO.mapOptional("mode", MFI.Mode, SIMode());
}
};
Modified: llvm/trunk/test/CodeGen/AMDGPU/omod-nsz-flag.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/omod-nsz-flag.mir?rev=365653&r1=365652&r2=365653&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/omod-nsz-flag.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/omod-nsz-flag.mir Wed Jul 10 09:09:26 2019
@@ -1,20 +1,5 @@
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
---- |
- define amdgpu_ps void @omod_inst_flag_nsz_src() {
- unreachable
- }
-
- define amdgpu_ps void @omod_inst_flag_nsz_result() {
- unreachable
- }
-
- define amdgpu_ps void @omod_inst_flag_nsz_both() {
- unreachable
- }
-
-...
-
---
# FIXME: Is it OK to fold omod for this?
@@ -24,6 +9,9 @@
# GCN-NEXT: S_ENDPGM 0, implicit %1
name: omod_inst_flag_nsz_src
tracksRegLiveness: true
+machineFunctionInfo:
+ mode:
+ ieee: false
body: |
bb.0:
@@ -42,6 +30,9 @@ body: |
name: omod_inst_flag_nsz_result
tracksRegLiveness: true
+machineFunctionInfo:
+ mode:
+ ieee: false
body: |
bb.0:
@@ -60,6 +51,9 @@ body: |
name: omod_inst_flag_nsz_both
tracksRegLiveness: true
+machineFunctionInfo:
+ mode:
+ ieee: false
body: |
bb.0:
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir?rev=365653&r1=365652&r2=365653&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir Wed Jul 10 09:09:26 2019
@@ -22,6 +22,9 @@
# FULL-NEXT: workGroupIDX: { reg: '$sgpr6' }
# FULL-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' }
# FULL-NEXT: workItemIDX: { reg: '$vgpr0' }
+# FULL-NEXT: mode:
+# FULL-NEXT: ieee: true
+# FULL-NEXT: dx10-clamp: true
# FULL-NEXT: body:
# SIMPLE: machineFunctionInfo:
@@ -85,6 +88,9 @@ body: |
# FULL-NEXT: argumentInfo:
# FULL-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
# FULL-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' }
+# FULL-NEXT: mode:
+# FULL-NEXT: ieee: true
+# FULL-NEXT: dx10-clamp: true
# FULL-NEXT: body:
# SIMPLE: machineFunctionInfo:
@@ -117,6 +123,9 @@ body: |
# FULL-NEXT: argumentInfo:
# FULL-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
# FULL-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' }
+# FULL-NEXT: mode:
+# FULL-NEXT: ieee: true
+# FULL-NEXT: dx10-clamp: true
# FULL-NEXT: body:
# SIMPLE: machineFunctionInfo:
@@ -150,6 +159,9 @@ body: |
# FULL-NEXT: argumentInfo:
# FULL-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
# FULL-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' }
+# FULL-NEXT: mode:
+# FULL-NEXT: ieee: true
+# FULL-NEXT: dx10-clamp: true
# FULL-NEXT: body:
# SIMPLE: machineFunctionInfo:
@@ -211,6 +223,23 @@ machineFunctionInfo:
body: |
bb.0:
+ S_ENDPGM 0
+
+...
+
+---
+# ALL-LABEL: name: parse_mode
+# ALL: mode:
+# ALL-NEXT: ieee: false
+# ALL-NEXT: dx10-clamp: false
+name: parse_mode
+machineFunctionInfo:
+ mode:
+ ieee: false
+ dx10-clamp: false
+
+body: |
+ bb.0:
S_ENDPGM 0
...
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll?rev=365653&r1=365652&r2=365653&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll (original)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll Wed Jul 10 09:09:26 2019
@@ -25,6 +25,9 @@
; CHECK-NEXT: workGroupIDX: { reg: '$sgpr6' }
; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' }
; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' }
+; CHECK-NEXT: mode:
+; CHECK-NEXT: ieee: true
+; CHECK-NEXT: dx10-clamp: true
; CHECK-NEXT: body:
define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) {
%gep = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %arg0
@@ -48,6 +51,9 @@ define amdgpu_kernel void @kernel(i32 %a
; CHECK-NEXT: argumentInfo:
; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr3' }
; CHECK-NEXT: implicitBufferPtr: { reg: '$sgpr0_sgpr1' }
+; CHECK-NEXT: mode:
+; CHECK-NEXT: ieee: false
+; CHECK-NEXT: dx10-clamp: true
; CHECK-NEXT: body:
define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) {
ret void
@@ -69,6 +75,9 @@ define amdgpu_ps void @ps_shader(i32 %ar
; CHECK-NEXT: argumentInfo:
; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' }
+; CHECK-NEXT: mode:
+; CHECK-NEXT: ieee: true
+; CHECK-NEXT: dx10-clamp: true
; CHECK-NEXT: body:
define void @function() {
ret void
@@ -90,9 +99,40 @@ define void @function() {
; CHECK-NEXT: argumentInfo:
; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' }
+; CHECK-NEXT: mode:
+; CHECK-NEXT: ieee: true
+; CHECK-NEXT: dx10-clamp: true
; CHECK-NEXT: body:
define void @function_nsz() #0 {
ret void
}
+; CHECK-LABEL: {{^}}name: function_dx10_clamp_off
+; CHECK: mode:
+; CHECK-NEXT: ieee: true
+; CHECK-NEXT: dx10-clamp: false
+define void @function_dx10_clamp_off() #1 {
+ ret void
+}
+
+; CHECK-LABEL: {{^}}name: function_ieee_off
+; CHECK: mode:
+; CHECK-NEXT: ieee: false
+; CHECK-NEXT: dx10-clamp: true
+define void @function_ieee_off() #2 {
+ ret void
+}
+
+; CHECK-LABEL: {{^}}name: function_ieee_off_dx10_clamp_off
+; CHECK: mode:
+; CHECK-NEXT: ieee: false
+; CHECK-NEXT: dx10-clamp: false
+define void @function_ieee_off_dx10_clamp_off() #3 {
+ ret void
+}
+
attributes #0 = { "no-signed-zeros-fp-math" = "true" }
+
+attributes #1 = { "amdgpu-dx10-clamp" = "false" }
+attributes #2 = { "amdgpu-ieee" = "false" }
+attributes #3 = { "amdgpu-dx10-clamp" = "false" "amdgpu-ieee" = "false" }
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