[PATCH] D64177: GlobalISel: fewerElementsVector for G_TRUNC

[Matt Arsenault via Phabricator via llvm-commits]

arsenm marked an inline comment as done.
arsenm added inline comments.


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Comment at: test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir:64
     ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
-    ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
-    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY]](<2 x s32>)
-    ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[TRUNC]], [[BUILD_VECTOR]](<2 x s16>)
-    ; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s16>)
-    ; CHECK: $vgpr0 = COPY [[ASHR]](<2 x s16>)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
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arsenm wrote:
> arsenm wrote:
> > aemerson wrote:
> > > Test still worthwhile having given it's now just a scalar artifact combine?
> > I'm not even sure this patch is the right way to go. I'm still not 100% sure how to get the artifacts into the end state I want while maintaining valid MIR at every step. I had to drop this patch and make all vector truncates legal to get my G_BUILD_VECTOR lowerings to not infinite loop. Declaring every vector truncate legal almost kind of works assuming every use is legalized, but fails in some degenerate cases (like an implicit use on a target instruction)
> I think D64436 avoids these issues, so scalarizing trunc should work
Maybe not, I'm still seeing some of these loops in another one of my branches


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D64177/new/

https://reviews.llvm.org/D64177