[PATCH] D64186: [NewPM] Port MachineDominatorTree analysis to the new PM.

[Charles Zhang via Phabricator via llvm-commits]

czhang updated this revision to Diff 208730.
czhang added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D64186/new/

https://reviews.llvm.org/D64186

Files:
  llvm/include/llvm/CodeGen/MachineDominators.h
  llvm/include/llvm/CodeGen/MachinePipeliner.h
  llvm/include/llvm/InitializePasses.h
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/CodeGen.cpp
  llvm/lib/CodeGen/EarlyIfConversion.cpp
  llvm/lib/CodeGen/InlineSpiller.cpp
  llvm/lib/CodeGen/LazyMachineBlockFrequencyInfo.cpp
  llvm/lib/CodeGen/LiveDebugVariables.cpp
  llvm/lib/CodeGen/LiveIntervals.cpp
  llvm/lib/CodeGen/MachineBasicBlock.cpp
  llvm/lib/CodeGen/MachineCSE.cpp
  llvm/lib/CodeGen/MachineCombiner.cpp
  llvm/lib/CodeGen/MachineDominanceFrontier.cpp
  llvm/lib/CodeGen/MachineDominators.cpp
  llvm/lib/CodeGen/MachineLICM.cpp
  llvm/lib/CodeGen/MachineLoopInfo.cpp
  llvm/lib/CodeGen/MachinePipeliner.cpp
  llvm/lib/CodeGen/MachineRegionInfo.cpp
  llvm/lib/CodeGen/MachineScheduler.cpp
  llvm/lib/CodeGen/MachineSink.cpp
  llvm/lib/CodeGen/PHIElimination.cpp
  llvm/lib/CodeGen/PeepholeOptimizer.cpp
  llvm/lib/CodeGen/PostRASchedulerList.cpp
  llvm/lib/CodeGen/PrologEpilogInserter.cpp
  llvm/lib/CodeGen/RegAllocBasic.cpp
  llvm/lib/CodeGen/RegAllocGreedy.cpp
  llvm/lib/CodeGen/RegAllocPBQP.cpp
  llvm/lib/CodeGen/ShrinkWrap.cpp
  llvm/lib/CodeGen/UnreachableBlockElim.cpp
  llvm/lib/CodeGen/XRayInstrumentation.cpp
  llvm/lib/Passes/PassRegistry.def
  llvm/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
  llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
  llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
  llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp
  llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
  llvm/lib/Target/AMDGPU/R600Packetizer.cpp
  llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/ARC/ARCBranchFinalize.cpp
  llvm/lib/Target/ARC/ARCOptAddrMode.cpp
  llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
  llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
  llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
  llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
  llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
  llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
  llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
  llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
  llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
  llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp
  llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
  llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
  llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp
  llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
  llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
  llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
  llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
  llvm/lib/Target/SystemZ/SystemZLDCleanup.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
  llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp

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