[llvm] r365506 - [NFC] Fixed tests
David Bolvansky via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 9 08:31:37 PDT 2019
Author: xbolva00
Date: Tue Jul 9 08:31:36 2019
New Revision: 365506
URL: http://llvm.org/viewvc/llvm-project?rev=365506&view=rev
Log:
[NFC] Fixed tests
Modified:
llvm/trunk/test/Transforms/InstSimplify/ashr-lshr.ll
Modified: llvm/trunk/test/Transforms/InstSimplify/ashr-lshr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/ashr-lshr.ll?rev=365506&r1=365505&r2=365506&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/ashr-lshr.ll (original)
+++ llvm/trunk/test/Transforms/InstSimplify/ashr-lshr.ll Tue Jul 9 08:31:36 2019
@@ -1,34 +1,43 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -instcombine -S | FileCheck %s
+; RUN: opt < %s -instsimplify -S | FileCheck %s
-define i32 @ashr_lshr_abs(i32 %x, i32 %y) {
-; CHECK-LABEL: @ashr_lshr_abs(
-; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret i32 [[R]]
+define i32 @ashr_lshr(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_lshr(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
+; CHECK-NEXT: ret i32 [[RET]]
;
- %cmp = icmp sge i32 %x, 0
+ %cmp = icmp sgt i32 %x, -1
%l = lshr i32 %x, %y
%r = ashr i32 %x, %y
%ret = select i1 %cmp, i32 %l, i32 %r
ret i32 %ret
}
-define i32 @ashr_lshr_abs_both_exact(i32 %x, i32 %y) {
-; CHECK-LABEL: @ashr_lshr_abs(
-; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret i32 [[R]]
+define i32 @ashr_lshr_exact(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_lshr_exact(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT: [[L:%.*]] = lshr exact i32 [[X]], [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
+; CHECK-NEXT: ret i32 [[RET]]
;
- %cmp = icmp sge i32 %x, 0
+ %cmp = icmp sgt i32 %x, -1
%l = lshr exact i32 %x, %y
%r = ashr exact i32 %x, %y
%ret = select i1 %cmp, i32 %l, i32 %r
ret i32 %ret
}
-define i32 @ashr_lshr_abs2(i32 %x, i32 %y) {
-; CHECK-LABEL: @ashr_lshr_abs2(
-; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret i32 [[R]]
+define i32 @ashr_lshr2(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_lshr2(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
+; CHECK-NEXT: ret i32 [[RET]]
;
%cmp = icmp sgt i32 %x, -1
%l = lshr i32 %x, %y
@@ -37,34 +46,58 @@ define i32 @ashr_lshr_abs2(i32 %x, i32 %
ret i32 %ret
}
-define <2 x i32> @ashr_lshr_abs_vec(<2 x i32> %x, <2 x i32> %y) {
-; CHECK-LABEL: @ashr_lshr_abs_vec(
-; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret <2 x i32> [[R]]
+define <2 x i32> @ashr_lshr_vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_vec(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
+; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
+; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
+; CHECK-NEXT: ret <2 x i32> [[RET]]
;
- %cmp = icmp sge <2 x i32> %x, zeroinitializer
+ %cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
%l = lshr <2 x i32> %x, %y
%r = ashr <2 x i32> %x, %y
%ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
ret <2 x i32> %ret
}
-define i32 @ashr_lshr_nabs2(i32 %x, i32 %y) {
-; CHECK-LABEL: @ashr_lshr_nabs2(
-; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret i32 [[R]]
+define <2 x i32> @ashr_lshr_vec2(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_vec2(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 undef, i32 -1>
+; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
+; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
+; CHECK-NEXT: ret <2 x i32> [[RET]]
;
- %cmp = icmp sle i32 %x, 0
- %l = lshr i32 %x, %y
- %r = ashr i32 %x, %y
- %ret = select i1 %cmp, i32 %r, i32 %l
- ret i32 %ret
+ %cmp = icmp sgt <2 x i32> %x, <i32 undef, i32 -1>
+ %l = lshr <2 x i32> %x, %y
+ %r = ashr <2 x i32> %x, %y
+ %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
+ ret <2 x i32> %ret
+}
+
+define <2 x i32> @ashr_lshr_vec3(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_vec3(
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 1, i32 undef>
+; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
+; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
+; CHECK-NEXT: ret <2 x i32> [[RET]]
+;
+ %cmp = icmp slt <2 x i32> %x, <i32 1, i32 undef>
+ %l = lshr <2 x i32> %x, %y
+ %r = ashr <2 x i32> %x, %y
+ %ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
+ ret <2 x i32> %ret
}
-define i32 @ashr_lshr_nabs(i32 %x, i32 %y) {
-; CHECK-LABEL: @ashr_lshr_nabs(
-; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret i32 [[R]]
+define i32 @ashr_lshr_inv(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_lshr_inv(
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 1
+; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
+; CHECK-NEXT: ret i32 [[RET]]
;
%cmp = icmp slt i32 %x, 1
%l = lshr i32 %x, %y
@@ -73,24 +106,56 @@ define i32 @ashr_lshr_nabs(i32 %x, i32 %
ret i32 %ret
}
-define <2 x i32> @ashr_lshr_nabs_vec(<2 x i32> %x, <2 x i32> %y) {
-; CHECK-LABEL: @ashr_lshr_nabs_vec(
-; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret <2 x i32> [[R]]
+define <2 x i32> @ashr_lshr_inv_vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_inv_vec(
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 1, i32 1>
+; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
+; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
+; CHECK-NEXT: ret <2 x i32> [[RET]]
;
- %cmp = icmp sle <2 x i32> %x, zeroinitializer
+ %cmp = icmp slt <2 x i32> %x, <i32 1, i32 1>
%l = lshr <2 x i32> %x, %y
%r = ashr <2 x i32> %x, %y
%ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
ret <2 x i32> %ret
}
+define i32 @ashr_lshr_exact_mismatch(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_lshr_exact_mismatch(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %cmp = icmp sgt i32 %x, -1
+ %l = lshr i32 %x, %y
+ %r = ashr exact i32 %x, %y
+ %ret = select i1 %cmp, i32 %l, i32 %r
+ ret i32 %ret
+}
+
+define i32 @ashr_lshr_exact_mismatch2(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_lshr_exact_mismatch2(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT: [[L:%.*]] = lshr exact i32 [[X]], [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %cmp = icmp sgt i32 %x, -1
+ %l = lshr exact i32 %x, %y
+ %r = ashr i32 %x, %y
+ %ret = select i1 %cmp, i32 %l, i32 %r
+ ret i32 %ret
+}
; Negative tests
-define i32 @ashr_lshr_wrong_abs(i32 %x, i32 %y) {
-; CHECK-LABEL: @ashr_lshr_wrong_abs(
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -2
+define i32 @ashr_lshr_wrong(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_lshr_wrong(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], -1
; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
@@ -103,9 +168,9 @@ define i32 @ashr_lshr_wrong_abs(i32 %x,
ret i32 %ret
}
-define i32 @ashr_lshr_abs_shift_wrong_pred(i32 %x, i32 %y, i32 %z) {
-; CHECK-LABEL: @ashr_lshr_abs_shift_wrong_pred(
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 1
+define i32 @ashr_lshr_shift_wrong_pred(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @ashr_lshr_shift_wrong_pred(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[X:%.*]], 0
; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
@@ -118,9 +183,9 @@ define i32 @ashr_lshr_abs_shift_wrong_pr
ret i32 %ret
}
-define i32 @ashr_lshr_abs_shift_wrong_pred2(i32 %x, i32 %y, i32 %z) {
-; CHECK-LABEL: @ashr_lshr_abs_shift_wrong_pred2(
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[Z:%.*]], -1
+define i32 @ashr_lshr_shift_wrong_pred2(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @ashr_lshr_shift_wrong_pred2(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[Z:%.*]], 0
; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
@@ -133,9 +198,9 @@ define i32 @ashr_lshr_abs_shift_wrong_pr
ret i32 %ret
}
-define i32 @ashr_lshr_abs_wrong_operands(i32 %x, i32 %y) {
-; CHECK-LABEL: @ashr_lshr_abs_wrong_operands(
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
+define i32 @ashr_lshr_wrong_operands(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_lshr_wrong_operands(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], 0
; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
@@ -148,9 +213,9 @@ define i32 @ashr_lshr_abs_wrong_operands
ret i32 %ret
}
-define i32 @ashr_lshr_abs_no_ashr(i32 %x, i32 %y) {
-; CHECK-LABEL: @ashr_lshr_abs_no_ashr(
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
+define i32 @ashr_lshr_no_ashr(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_lshr_no_ashr(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], 0
; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = xor i32 [[X]], [[Y]]
; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
@@ -163,9 +228,9 @@ define i32 @ashr_lshr_abs_no_ashr(i32 %x
ret i32 %ret
}
-define i32 @ashr_lshr_abs_shift_amt_mismatch(i32 %x, i32 %y, i32 %z) {
-; CHECK-LABEL: @ashr_lshr_abs_shift_amt_mismatch(
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
+define i32 @ashr_lshr_shift_amt_mismatch(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @ashr_lshr_shift_amt_mismatch(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], 0
; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Z:%.*]]
; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
@@ -178,9 +243,9 @@ define i32 @ashr_lshr_abs_shift_amt_mism
ret i32 %ret
}
-define i32 @ashr_lshr_abs_shift_base_mismatch(i32 %x, i32 %y, i32 %z) {
-; CHECK-LABEL: @ashr_lshr_abs_shift_base_mismatch(
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
+define i32 @ashr_lshr_shift_base_mismatch(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @ashr_lshr_shift_base_mismatch(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], 0
; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = ashr i32 [[Z:%.*]], [[Y]]
; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
@@ -193,9 +258,9 @@ define i32 @ashr_lshr_abs_shift_base_mis
ret i32 %ret
}
-define i32 @ashr_lshr_abs_no_lshr(i32 %x, i32 %y) {
-; CHECK-LABEL: @ashr_lshr_abs_no_lshr(
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
+define i32 @ashr_lshr_no_lshr(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_lshr_no_lshr(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], 0
; CHECK-NEXT: [[L:%.*]] = add i32 [[X]], [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
@@ -208,9 +273,9 @@ define i32 @ashr_lshr_abs_no_lshr(i32 %x
ret i32 %ret
}
-define <2 x i32> @ashr_lshr_abs_vec_wrong_pred(<2 x i32> %x, <2 x i32> %y) {
-; CHECK-LABEL: @ashr_lshr_abs_vec_wrong_pred(
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 1, i32 1>
+define <2 x i32> @ashr_lshr_vec_wrong_pred(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_vec_wrong_pred(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sle <2 x i32> [[X:%.*]], zeroinitializer
; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
@@ -223,9 +288,9 @@ define <2 x i32> @ashr_lshr_abs_vec_wron
ret <2 x i32> %ret
}
-define <2 x i32> @ashr_lshr_nabs_vec_wrong_pred(<2 x i32> %x, <2 x i32> %y) {
-; CHECK-LABEL: @ashr_lshr_nabs_vec_wrong_pred(
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
+define <2 x i32> @ashr_lshr_inv_vec_wrong_pred(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_inv_vec_wrong_pred(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sge <2 x i32> [[X:%.*]], zeroinitializer
; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
@@ -237,4 +302,3 @@ define <2 x i32> @ashr_lshr_nabs_vec_wro
%ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
ret <2 x i32> %ret
}
-
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