[llvm] r365501 - [NFC] Added tests for D64285

David Bolvansky via llvm-commits llvm-commits at lists.llvm.org
Tue Jul 9 08:12:02 PDT 2019


Author: xbolva00
Date: Tue Jul  9 08:12:01 2019
New Revision: 365501

URL: http://llvm.org/viewvc/llvm-project?rev=365501&view=rev
Log:
[NFC] Added tests for D64285

Added:
    llvm/trunk/test/Transforms/InstSimplify/ashr-lshr.ll

Added: llvm/trunk/test/Transforms/InstSimplify/ashr-lshr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/ashr-lshr.ll?rev=365501&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/ashr-lshr.ll (added)
+++ llvm/trunk/test/Transforms/InstSimplify/ashr-lshr.ll Tue Jul  9 08:12:01 2019
@@ -0,0 +1,240 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define i32 @ashr_lshr_abs(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_lshr_abs(
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %cmp = icmp sge i32 %x, 0
+  %l = lshr i32 %x, %y
+  %r = ashr i32 %x, %y
+  %ret = select i1 %cmp, i32 %l, i32 %r
+  ret i32 %ret
+}
+
+define i32 @ashr_lshr_abs_both_exact(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_lshr_abs(
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %cmp = icmp sge i32 %x, 0
+  %l = lshr exact i32 %x, %y
+  %r = ashr exact i32 %x, %y
+  %ret = select i1 %cmp, i32 %l, i32 %r
+  ret i32 %ret
+}
+
+define i32 @ashr_lshr_abs2(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_lshr_abs2(
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %cmp = icmp sgt i32 %x, -1
+  %l = lshr i32 %x, %y
+  %r = ashr i32 %x, %y
+  %ret = select i1 %cmp, i32 %l, i32 %r
+  ret i32 %ret
+}
+
+define <2 x i32> @ashr_lshr_abs_vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_abs_vec(
+; CHECK-NEXT:    [[R:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %cmp = icmp sge <2 x i32> %x, zeroinitializer
+  %l = lshr <2 x i32> %x, %y
+  %r = ashr <2 x i32> %x, %y
+  %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
+  ret <2 x i32> %ret
+}
+
+define i32 @ashr_lshr_nabs2(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_lshr_nabs2(
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %cmp = icmp sle i32 %x, 0
+  %l = lshr i32 %x, %y
+  %r = ashr i32 %x, %y
+  %ret = select i1 %cmp, i32 %r, i32 %l
+  ret i32 %ret
+}
+
+define i32 @ashr_lshr_nabs(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_lshr_nabs(
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %cmp = icmp slt i32 %x, 1
+  %l = lshr i32 %x, %y
+  %r = ashr i32 %x, %y
+  %ret = select i1 %cmp, i32 %r, i32 %l
+  ret i32 %ret
+}
+
+define <2 x i32> @ashr_lshr_nabs_vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_nabs_vec(
+; CHECK-NEXT:    [[R:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %cmp = icmp sle <2 x i32> %x, zeroinitializer
+  %l = lshr <2 x i32> %x, %y
+  %r = ashr <2 x i32> %x, %y
+  %ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
+  ret <2 x i32> %ret
+}
+
+
+; Negative tests
+
+define i32 @ashr_lshr_wrong_abs(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_lshr_wrong_abs(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -2
+; CHECK-NEXT:    [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X]], [[Y]]
+; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
+; CHECK-NEXT:    ret i32 [[RET]]
+;
+  %cmp = icmp sge i32 %x, -1
+  %l = lshr i32 %x, %y
+  %r = ashr i32 %x, %y
+  %ret = select i1 %cmp, i32 %l, i32 %r
+  ret i32 %ret
+}
+
+define i32 @ashr_lshr_abs_shift_wrong_pred(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @ashr_lshr_abs_shift_wrong_pred(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 1
+; CHECK-NEXT:    [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X]], [[Y]]
+; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
+; CHECK-NEXT:    ret i32 [[RET]]
+;
+  %cmp = icmp sle i32 %x, 0
+  %l = lshr i32 %x, %y
+  %r = ashr i32 %x, %y
+  %ret = select i1 %cmp, i32 %l, i32 %r
+  ret i32 %ret
+}
+
+define i32 @ashr_lshr_abs_shift_wrong_pred2(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @ashr_lshr_abs_shift_wrong_pred2(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[Z:%.*]], -1
+; CHECK-NEXT:    [[L:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X]], [[Y]]
+; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
+; CHECK-NEXT:    ret i32 [[RET]]
+;
+  %cmp = icmp sge i32 %z, 0
+  %l = lshr i32 %x, %y
+  %r = ashr i32 %x, %y
+  %ret = select i1 %cmp, i32 %l, i32 %r
+  ret i32 %ret
+}
+
+define i32 @ashr_lshr_abs_wrong_operands(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_lshr_abs_wrong_operands(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT:    [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X]], [[Y]]
+; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
+; CHECK-NEXT:    ret i32 [[RET]]
+;
+  %cmp = icmp sge i32 %x, 0
+  %l = lshr i32 %x, %y
+  %r = ashr i32 %x, %y
+  %ret = select i1 %cmp, i32 %r, i32 %l
+  ret i32 %ret
+}
+
+define i32 @ashr_lshr_abs_no_ashr(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_lshr_abs_no_ashr(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT:    [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = xor i32 [[X]], [[Y]]
+; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
+; CHECK-NEXT:    ret i32 [[RET]]
+;
+  %cmp = icmp sge i32 %x, 0
+  %l = lshr i32 %x, %y
+  %r = xor i32 %x, %y
+  %ret = select i1 %cmp, i32 %l, i32 %r
+  ret i32 %ret
+}
+
+define i32 @ashr_lshr_abs_shift_amt_mismatch(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @ashr_lshr_abs_shift_amt_mismatch(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT:    [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
+; CHECK-NEXT:    ret i32 [[RET]]
+;
+  %cmp = icmp sge i32 %x, 0
+  %l = lshr i32 %x, %y
+  %r = ashr i32 %x, %z
+  %ret = select i1 %cmp, i32 %l, i32 %r
+  ret i32 %ret
+}
+
+define i32 @ashr_lshr_abs_shift_base_mismatch(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @ashr_lshr_abs_shift_base_mismatch(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT:    [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[Z:%.*]], [[Y]]
+; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
+; CHECK-NEXT:    ret i32 [[RET]]
+;
+  %cmp = icmp sge i32 %x, 0
+  %l = lshr i32 %x, %y
+  %r = ashr i32 %z, %y
+  %ret = select i1 %cmp, i32 %l, i32 %r
+  ret i32 %ret
+}
+
+define i32 @ashr_lshr_abs_no_lshr(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_lshr_abs_no_lshr(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT:    [[L:%.*]] = add i32 [[X]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X]], [[Y]]
+; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
+; CHECK-NEXT:    ret i32 [[RET]]
+;
+  %cmp = icmp sge i32 %x, 0
+  %l = add i32 %x, %y
+  %r = ashr i32 %x, %y
+  %ret = select i1 %cmp, i32 %l, i32 %r
+  ret i32 %ret
+}
+
+define <2 x i32> @ashr_lshr_abs_vec_wrong_pred(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_abs_vec_wrong_pred(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 1, i32 1>
+; CHECK-NEXT:    [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
+; CHECK-NEXT:    [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
+; CHECK-NEXT:    ret <2 x i32> [[RET]]
+;
+  %cmp = icmp sle <2 x i32> %x, zeroinitializer
+  %l = lshr <2 x i32> %x, %y
+  %r = ashr <2 x i32> %x, %y
+  %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
+  ret <2 x i32> %ret
+}
+
+define <2 x i32> @ashr_lshr_nabs_vec_wrong_pred(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_nabs_vec_wrong_pred(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
+; CHECK-NEXT:    [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
+; CHECK-NEXT:    [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
+; CHECK-NEXT:    ret <2 x i32> [[RET]]
+;
+  %cmp = icmp sge <2 x i32> %x, zeroinitializer
+  %l = lshr <2 x i32> %x, %y
+  %r = ashr <2 x i32> %x, %y
+  %ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
+  ret <2 x i32> %ret
+}
+




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