[llvm] r365493 - AMDGPU/GlobalISel: Prepare some tests for store selection
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 9 07:30:58 PDT 2019
Author: arsenm
Date: Tue Jul 9 07:30:57 2019
New Revision: 365493
URL: http://llvm.org/viewvc/llvm-project?rev=365493&view=rev
Log:
AMDGPU/GlobalISel: Prepare some tests for store selection
Mostsly these would fail due to trying to use SI with a flat
operation. Implementing global loads with MUBUF is more work than
flat, so these won't be handled in the initial load selection.
Others fail because store of s64 won't initially work, as the current
set of patterns expect everything to be turned into v2i32.
Modified:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-maxnum.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-minnum.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir?rev=365493&r1=365492&r2=365493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir Tue Jul 9 07:30:57 2019
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
@@ -11,27 +12,25 @@ body: |
bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
+
; GFX6-LABEL: name: add_s32
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; GFX6: [[S_ADD_U32_:%[0-9]+]]:sreg_32_xm0 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX6: %7:vgpr_32, dead %12:sreg_64_xexec = V_ADD_I32_e64 [[COPY2]], [[S_ADD_U32_]], 0, implicit $exec
; GFX6: %8:vgpr_32, dead %11:sreg_64_xexec = V_ADD_I32_e64 [[S_ADD_U32_]], %7, 0, implicit $exec
; GFX6: %9:vgpr_32, dead %10:sreg_64_xexec = V_ADD_I32_e64 %8, [[COPY2]], 0, implicit $exec
- ; GFX6: FLAT_STORE_DWORD [[COPY3]], %9, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
+ ; GFX6: S_ENDPGM 0, implicit %9
; GFX9-LABEL: name: add_s32
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX9: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32_xm0 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[S_ADD_U32_]], 0, implicit $exec
; GFX9: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_ADD_U32_]], [[V_ADD_U32_e64_]], 0, implicit $exec
; GFX9: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_1]], [[COPY2]], 0, implicit $exec
- ; GFX9: FLAT_STORE_DWORD [[COPY3]], [[V_ADD_U32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
-
+ ; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_2]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:vgpr(s32) = COPY $vgpr0
@@ -51,6 +50,6 @@ body: |
; add vv
%9:vgpr(s32) = G_ADD %8, %2
- G_STORE %9, %3 :: (store 4, addrspace 1)
+ S_ENDPGM 0, implicit %9
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir?rev=365493&r1=365492&r2=365493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir Tue Jul 9 07:30:57 2019
@@ -1,9 +1,6 @@
-# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
---- |
- define void @cvt_pkrtz(i32 addrspace(1)* %global0) { ret void }
-...
---
name: cvt_pkrtz
@@ -38,8 +35,5 @@ body: |
%7:vgpr(s32) = G_BITCAST %4
%8:vgpr(s32) = G_BITCAST %5
%9:vgpr(s32) = G_BITCAST %6
- G_STORE %7, %3 :: (store 4 into %ir.global0, addrspace 1)
- G_STORE %8, %3 :: (store 4 into %ir.global0, addrspace 1)
- G_STORE %9, %3 :: (store 4 into %ir.global0, addrspace 1)
+ S_ENDPGM 0, implicit %7, implicit %8, implicit %9
...
----
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir?rev=365493&r1=365492&r2=365493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir Tue Jul 9 07:30:57 2019
@@ -1,9 +1,6 @@
-# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN,SI
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN,VI
+# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,SI
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,VI
---- |
- define void @ashr(i32 addrspace(1)* %global0) {ret void}
-...
---
name: ashr
@@ -80,7 +77,6 @@ body: |
%17:vgpr(s32) = G_ASHR %16, %5
- G_STORE %17, %3 :: (store 4 into %ir.global0, addrspace 1)
+ S_ENDPGM 0, implicit %17
...
----
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir?rev=365493&r1=365492&r2=365493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir Tue Jul 9 07:30:57 2019
@@ -1,26 +1,21 @@
-# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
---- |
- define amdgpu_kernel void @bitcast(i32 addrspace(1)* %global0) {ret void}
-...
---
name: bitcast
legalized: true
regBankSelected: true
+tracksRegLiveness: true
# GCN-LABEL: name: bitcast
# GCN: [[A:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-# GCN: [[B:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
-# GCN: FLAT_STORE_DWORD [[B]], [[A]]
+# GCN: S_ENDPGM 0, implicit [[A]]
body: |
bb.0:
- liveins: $sgpr0, $vgpr3_vgpr4
+ liveins: $vgpr0
%0:vgpr(s32) = COPY $vgpr0
- %1:vgpr(p1) = COPY $vgpr3_vgpr4
- %2:vgpr(<2 x s16>) = G_BITCAST %0
- %3:vgpr(s32) = G_BITCAST %2
- G_STORE %3, %1 :: (store 4 into %ir.global0, addrspace 1)
+ %1:vgpr(<2 x s16>) = G_BITCAST %0
+ %2:vgpr(s32) = G_BITCAST %1
+ S_ENDPGM 0, implicit %2
...
----
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir?rev=365493&r1=365492&r2=365493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir Tue Jul 9 07:30:57 2019
@@ -1,8 +1,5 @@
-# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
---- |
- define amdgpu_kernel void @constant(i32 addrspace(1)* %global0, i64 addrspace(1)* %global1) {ret void}
-...
---
name: constant
@@ -49,13 +46,7 @@ body: |
; GCN: %{{[0-9]+}}:vreg_64 = REG_SEQUENCE [[LO3]], %subreg.sub0, [[HI3]], %subreg.sub1
%9:vgpr(s64) = G_FCONSTANT double 1.0
- G_STORE %2, %0 :: (volatile store 4 into %ir.global0, addrspace 1)
- G_STORE %4, %0 :: (volatile store 4 into %ir.global0, addrspace 1)
- G_STORE %6, %0 :: (volatile store 4 into %ir.global0, addrspace 1)
- G_STORE %8, %0 :: (volatile store 4 into %ir.global0, addrspace 1)
- G_STORE %3, %1 :: (volatile store 8 into %ir.global1, addrspace 1)
- G_STORE %5, %1 :: (volatile store 8 into %ir.global1, addrspace 1)
- G_STORE %7, %1 :: (volatile store 8 into %ir.global1, addrspace 1)
- G_STORE %9, %1 :: (volatile store 8 into %ir.global1, addrspace 1)
+ S_ENDPGM 0, implicit %2, implicit %4, implicit %6, implicit %8, implicit %3, implicit %5, implicit %7, implicit %9
+
...
----
+
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir?rev=365493&r1=365492&r2=365493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir Tue Jul 9 07:30:57 2019
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel -o - %s | FileCheck -check-prefix=WAVE64 %s
-# RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -run-pass=instruction-select -verify-machineinstrs -global-isel -o - %s | FileCheck -check-prefix=WAVE32 %s
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE64 %s
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE32 %s
---
@@ -151,6 +151,13 @@ body: |
; GCN-LABEL: name: copy_sgpr_no_type
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
; GCN: S_ENDPGM 0, implicit [[COPY]]
+ ; WAVE64-LABEL: name: copy_sgpr_no_type
+ ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; WAVE64: S_ENDPGM 0, implicit [[COPY]]
+ ; WAVE32-LABEL: name: copy_sgpr_no_type
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; WAVE32: S_ENDPGM 0, implicit [[COPY]]
%0:sreg_32_xm0 = COPY $sgpr0
%1:sreg_32_xm0 = COPY %0
S_ENDPGM 0, implicit %1
@@ -170,6 +177,13 @@ body: |
; GCN-LABEL: name: copy_vgpr_no_type
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: S_ENDPGM 0, implicit [[COPY]]
+ ; WAVE64-LABEL: name: copy_vgpr_no_type
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: S_ENDPGM 0, implicit [[COPY]]
+ ; WAVE32-LABEL: name: copy_vgpr_no_type
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: S_ENDPGM 0, implicit [[COPY]]
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY %0
S_ENDPGM 0, implicit %1
@@ -189,6 +203,13 @@ body: |
; GCN-LABEL: name: copy_maybe_vcc
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
; GCN: S_ENDPGM 0, implicit [[COPY]]
+ ; WAVE64-LABEL: name: copy_maybe_vcc
+ ; WAVE64: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; WAVE64: S_ENDPGM 0, implicit [[COPY]]
+ ; WAVE32-LABEL: name: copy_maybe_vcc
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; WAVE32: S_ENDPGM 0, implicit [[COPY]]
%0:sreg_64_xexec = COPY $sgpr0_sgpr1
%1:sreg_64_xexec = COPY %0
S_ENDPGM 0, implicit %1
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir?rev=365493&r1=365492&r2=365493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir Tue Jul 9 07:30:57 2019
@@ -1,8 +1,5 @@
-# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
---- |
- define amdgpu_kernel void @fadd(i32 addrspace(1)* %global0) {ret void}
-...
---
name: fadd
@@ -30,8 +27,7 @@ body: |
; GCN: V_ADD_F32_e64
%6:vgpr(s32) = G_FADD %1, %2
- G_STORE %4, %3 :: (store 4 into %ir.global0)
- G_STORE %5, %3 :: (store 4 into %ir.global0)
- G_STORE %6, %3 :: (store 4 into %ir.global0)
+ G_STORE %4, %3 :: (store 4, addrspace 1)
+ G_STORE %5, %3 :: (store 4, addrspace 1)
+ G_STORE %6, %3 :: (store 4, addrspace 1)
...
----
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir?rev=365493&r1=365492&r2=365493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir Tue Jul 9 07:30:57 2019
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
---
@@ -53,13 +53,10 @@ body: |
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
- ; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
; GCN: [[V_MUL_F64_:%[0-9]+]]:vreg_64 = V_MUL_F64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
; GCN: [[V_MUL_F64_1:%[0-9]+]]:vreg_64 = V_MUL_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
; GCN: [[V_MUL_F64_2:%[0-9]+]]:vreg_64 = V_MUL_F64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
- ; GCN: FLAT_STORE_DWORDX2 [[COPY3]], [[V_MUL_F64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
- ; GCN: FLAT_STORE_DWORDX2 [[COPY3]], [[V_MUL_F64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
- ; GCN: FLAT_STORE_DWORDX2 [[COPY3]], [[V_MUL_F64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
+ ; GCN: S_ENDPGM 0, implicit [[V_MUL_F64_]], implicit [[V_MUL_F64_1]], implicit [[V_MUL_F64_2]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s64) = COPY $vgpr0_vgpr1
%2:vgpr(s64) = COPY $vgpr2_vgpr3
@@ -73,10 +70,8 @@ body: |
; fmul vv
%6:vgpr(s64) = G_FMUL %1, %2
+ S_ENDPGM 0, implicit %4, implicit %5, implicit %6
- G_STORE %4, %3 :: (store 8, addrspace 1)
- G_STORE %5, %3 :: (store 8, addrspace 1)
- G_STORE %6, %3 :: (store 8, addrspace 1)
...
---
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir?rev=365493&r1=365492&r2=365493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir Tue Jul 9 07:30:57 2019
@@ -1,8 +1,5 @@
-# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN
---- |
- define amdgpu_kernel void @fptoui(i32 addrspace(1)* %global0) {ret void}
-...
---
name: fptoui
@@ -30,7 +27,6 @@ body: |
; GCN: V_CVT_U32_F32_e64 0, [[VGPR]], 0, 0
%4:vgpr(s32) = G_FPTOUI %1
- G_STORE %3, %2 :: (store 4 into %ir.global0)
- G_STORE %4, %2 :: (store 4 into %ir.global0)
+ G_STORE %3, %2 :: (store 4, addrspace 1)
+ G_STORE %4, %2 :: (store 4, addrspace 1)
...
----
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir?rev=365493&r1=365492&r2=365493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir Tue Jul 9 07:30:57 2019
@@ -1,5 +1,5 @@
-# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
---
name: icmp_s32_s_mix
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir?rev=365493&r1=365492&r2=365493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir Tue Jul 9 07:30:57 2019
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefixes=GCN %s
-# XUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' -o /dev/null %s 2>&1 | FileCheck -check-prefixes=ERR %s
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefixes=GCN %s
+# XUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' -o /dev/null %s 2>&1 | FileCheck -check-prefixes=ERR %s
# G_IMPLICIT_DEF should probably never be produced for scc. Make sure there's no crash.
# ERR: remark: <unknown>:0:0: cannot select: %0:scc(s1) = G_IMPLICIT_DEF (in function: implicit_def_s1_scc)
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir?rev=365493&r1=365492&r2=365493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir Tue Jul 9 07:30:57 2019
@@ -1,8 +1,5 @@
-# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
---- |
- define amdgpu_kernel void @inttoptr(i32 addrspace(4)* %const0, i32 addrspace(0)* %flat0) {ret void}
-...
---
name: inttoptr
@@ -26,9 +23,8 @@ body: |
%0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s64) = COPY $vgpr0_vgpr1
%2:sgpr(p4) = G_INTTOPTR %0
- %3:sgpr(s32) = G_LOAD %2 :: (load 4 from %ir.const0)
+ %3:sgpr(s32) = G_LOAD %2 :: (load 4, addrspace 1)
%4:vgpr(p0) = G_INTTOPTR %1
%5:vgpr(s32) = COPY %3
- G_STORE %5, %4 :: (store 4 into %ir.flat0)
+ G_STORE %5, %4 :: (store 4, addrspace 1)
...
----
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-maxnum.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-maxnum.mir?rev=365493&r1=365492&r2=365493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-maxnum.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-maxnum.mir Tue Jul 9 07:30:57 2019
@@ -1,8 +1,5 @@
-# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
---- |
- define void @maxnum(i32 addrspace(1)* %global0) { ret void }
-...
---
name: maxnum
@@ -40,9 +37,9 @@ body: |
; GCN: V_MAX_F32_e32 [[VGPR0]], [[VGPR1]]
%6:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.maxnum.f32), %1, %2
- G_STORE %4, %3 :: (store 4 into %ir.global0)
- G_STORE %5, %3 :: (store 4 into %ir.global0)
- G_STORE %6, %3 :: (store 4 into %ir.global0)
+ G_STORE %4, %3 :: (store 4, addrspace 1)
+ G_STORE %5, %3 :: (store 4, addrspace 1)
+ G_STORE %6, %3 :: (store 4, addrspace 1)
; 64-bit
@@ -58,9 +55,6 @@ body: |
; GCN: V_MAX_F64 0, [[VGPR64_0]], 0, [[VGPR64_1]], 0, 0
%16:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.maxnum.f64), %11, %12
- G_STORE %14, %3 :: (store 8 into %ir.global0)
- G_STORE %15, %3 :: (store 8 into %ir.global0)
- G_STORE %16, %3 :: (store 8 into %ir.global0)
+ S_ENDPGM 0, implicit %14, implicit %15, implicit %16
...
----
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-minnum.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-minnum.mir?rev=365493&r1=365492&r2=365493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-minnum.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-minnum.mir Tue Jul 9 07:30:57 2019
@@ -1,8 +1,5 @@
-# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
---- |
- define void @minnum(i32 addrspace(1)* %global0) { ret void }
-...
---
name: minnum
@@ -40,9 +37,9 @@ body: |
; GCN: V_MIN_F32_e32 [[VGPR0]], [[VGPR1]]
%6:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.minnum.f32), %1, %2
- G_STORE %4, %3 :: (store 4 into %ir.global0)
- G_STORE %5, %3 :: (store 4 into %ir.global0)
- G_STORE %6, %3 :: (store 4 into %ir.global0)
+ G_STORE %4, %3 :: (store 4, addrspace 1)
+ G_STORE %5, %3 :: (store 4, addrspace 1)
+ G_STORE %6, %3 :: (store 4, addrspace 1)
; 64-bit
@@ -58,8 +55,5 @@ body: |
; GCN: V_MIN_F64 0, [[VGPR64_0]], 0, [[VGPR64_1]], 0, 0
%16:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.minnum.f64), %11, %12
- G_STORE %14, %3 :: (store 8 into %ir.global0)
- G_STORE %15, %3 :: (store 8 into %ir.global0)
- G_STORE %16, %3 :: (store 8 into %ir.global0)
+ S_ENDPGM 0, implicit %14, implicit %15, implicit %16
...
----
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir?rev=365493&r1=365492&r2=365493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir Tue Jul 9 07:30:57 2019
@@ -1,8 +1,5 @@
-# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
---- |
- define void @or(i32 addrspace(1)* %global0) {ret void}
-...
---
name: or
@@ -39,7 +36,6 @@ body: |
; GCN: [[VV:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[SV]], [[VGPR0]]
%9:vgpr(s32) = G_OR %8, %2
- G_STORE %9, %3 :: (store 4 into %ir.global0, addrspace 1)
+ G_STORE %9, %3 :: (store 4, addrspace 1)
...
----
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir?rev=365493&r1=365492&r2=365493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir Tue Jul 9 07:30:57 2019
@@ -1,8 +1,5 @@
-# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
---- |
- define amdgpu_kernel void @sitofp(i32 addrspace(1)* %global0) {ret void}
-...
---
name: sitofp
@@ -30,7 +27,6 @@ body: |
; GCN: V_CVT_F32_I32_e64 [[VGPR]], 0, 0
%4:vgpr(s32) = G_SITOFP %1
- G_STORE %3, %2 :: (store 4 into %ir.global0)
- G_STORE %4, %2 :: (store 4 into %ir.global0)
+ G_STORE %3, %2 :: (store 4, addrspace 1)
+ G_STORE %4, %2 :: (store 4, addrspace 1)
...
----
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir?rev=365493&r1=365492&r2=365493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir Tue Jul 9 07:30:57 2019
@@ -2,7 +2,7 @@
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
-# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
---
name: sub_s32
@@ -20,23 +20,32 @@ body: |
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; GFX6: [[S_SUB_U32_:%[0-9]+]]:sreg_32_xm0 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX6: %7:vgpr_32, dead %12:sreg_64_xexec = V_SUB_I32_e64 [[COPY2]], [[S_SUB_U32_]], 0, implicit $exec
; GFX6: %8:vgpr_32, dead %11:sreg_64_xexec = V_SUB_I32_e64 [[S_SUB_U32_]], %7, 0, implicit $exec
; GFX6: %9:vgpr_32, dead %10:sreg_64_xexec = V_SUB_I32_e64 %8, [[COPY2]], 0, implicit $exec
- ; GFX6: FLAT_STORE_DWORD [[COPY3]], %9, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
+ ; GFX6: S_ENDPGM 0, implicit %9
; GFX9-LABEL: name: sub_s32
; GFX9: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX9: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; GFX9: [[S_SUB_U32_:%[0-9]+]]:sreg_32_xm0 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX9: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY2]], [[S_SUB_U32_]], 0, implicit $exec
; GFX9: [[V_SUB_U32_e64_1:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[S_SUB_U32_]], [[V_SUB_U32_e64_]], 0, implicit $exec
; GFX9: [[V_SUB_U32_e64_2:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[V_SUB_U32_e64_1]], [[COPY2]], 0, implicit $exec
- ; GFX9: FLAT_STORE_DWORD [[COPY3]], [[V_SUB_U32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
+ ; GFX9: S_ENDPGM 0, implicit [[V_SUB_U32_e64_2]]
+ ; GFX10-LABEL: name: sub_s32
+ ; GFX10: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[S_SUB_U32_:%[0-9]+]]:sreg_32_xm0 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX10: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY2]], [[S_SUB_U32_]], 0, implicit $exec
+ ; GFX10: [[V_SUB_U32_e64_1:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[S_SUB_U32_]], [[V_SUB_U32_e64_]], 0, implicit $exec
+ ; GFX10: [[V_SUB_U32_e64_2:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[V_SUB_U32_e64_1]], [[COPY2]], 0, implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_SUB_U32_e64_2]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:vgpr(s32) = COPY $vgpr0
@@ -56,6 +65,6 @@ body: |
; sub vv
%9:vgpr(s32) = G_SUB %8, %2
- G_STORE %9, %3 :: (store 4, addrspace 1)
+ S_ENDPGM 0, implicit %9
...
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