[llvm] r365482 - AMDGPU/GlobalISel: Select G_MERGE_VALUES
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 9 07:02:21 PDT 2019
Author: arsenm
Date: Tue Jul 9 07:02:20 2019
New Revision: 365482
URL: http://llvm.org/viewvc/llvm-project?rev=365482&view=rev
Log:
AMDGPU/GlobalISel: Select G_MERGE_VALUES
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp?rev=365482&r1=365481&r2=365482&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp Tue Jul 9 07:02:20 2019
@@ -325,6 +325,44 @@ bool AMDGPUInstructionSelector::selectG_
return true;
}
+bool AMDGPUInstructionSelector::selectG_MERGE_VALUES(MachineInstr &MI) const {
+ MachineBasicBlock *BB = MI.getParent();
+ MachineFunction *MF = BB->getParent();
+ MachineRegisterInfo &MRI = MF->getRegInfo();
+ Register DstReg = MI.getOperand(0).getReg();
+ LLT DstTy = MRI.getType(DstReg);
+ LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
+
+ const unsigned SrcSize = SrcTy.getSizeInBits();
+ const DebugLoc &DL = MI.getDebugLoc();
+ const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, TRI);
+ const unsigned DstSize = DstTy.getSizeInBits();
+ const TargetRegisterClass *DstRC =
+ TRI.getRegClassForSizeOnBank(DstSize, *DstBank, MRI);
+ if (!DstRC)
+ return false;
+
+ ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(DstRC, SrcSize / 8);
+ MachineInstrBuilder MIB =
+ BuildMI(*BB, &MI, DL, TII.get(TargetOpcode::REG_SEQUENCE), DstReg);
+ for (int I = 0, E = MI.getNumOperands() - 1; I != E; ++I) {
+ MachineOperand &Src = MI.getOperand(I + 1);
+ MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef()));
+ MIB.addImm(SubRegs[I]);
+
+ const TargetRegisterClass *SrcRC
+ = TRI.getConstrainedRegClassForOperand(Src, MRI);
+ if (SrcRC && !RBI.constrainGenericRegister(Src.getReg(), *SrcRC, MRI))
+ return false;
+ }
+
+ if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI))
+ return false;
+
+ MI.eraseFromParent();
+ return true;
+}
+
bool AMDGPUInstructionSelector::selectG_GEP(MachineInstr &I) const {
return selectG_ADD(I);
}
@@ -1144,6 +1182,9 @@ bool AMDGPUInstructionSelector::select(M
return selectG_CONSTANT(I);
case TargetOpcode::G_EXTRACT:
return selectG_EXTRACT(I);
+ case TargetOpcode::G_MERGE_VALUES:
+ case TargetOpcode::G_CONCAT_VECTORS:
+ return selectG_MERGE_VALUES(I);
case TargetOpcode::G_GEP:
return selectG_GEP(I);
case TargetOpcode::G_IMPLICIT_DEF:
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h?rev=365482&r1=365481&r2=365482&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h Tue Jul 9 07:02:20 2019
@@ -75,6 +75,7 @@ private:
bool selectG_CONSTANT(MachineInstr &I) const;
bool selectG_ADD(MachineInstr &I) const;
bool selectG_EXTRACT(MachineInstr &I) const;
+ bool selectG_MERGE_VALUES(MachineInstr &I) const;
bool selectG_GEP(MachineInstr &I) const;
bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
bool selectG_INSERT(MachineInstr &I) const;
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=365482&r1=365481&r2=365482&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Tue Jul 9 07:02:20 2019
@@ -641,7 +641,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
Query.Types[0].getScalarSizeInBits() == 64;
});
- // TODO: Support any combination of v2s32
+ // TODO: Support any combination of s16, s32, s64, pointer vectors.
getActionDefinitionsBuilder(G_CONCAT_VECTORS)
.legalFor({{V4S32, V2S32},
{V8S32, V2S32},
@@ -651,7 +651,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
{V8S16, V2S16},
{V8S16, V4S16},
{LLT::vector(4, LocalPtr), LLT::vector(2, LocalPtr)},
- {LLT::vector(4, PrivatePtr), LLT::vector(2, PrivatePtr)}});
+ {LLT::vector(4, PrivatePtr), LLT::vector(2, PrivatePtr)}})
+ // FIXME: Should restrict maximum size, but there seems to be a missing predicate.
+ .legalIf(typeInSet(1, {V2S32, V4S32, V8S32,V2S16, V4S16, V8S16, LLT::vector(16, 16), V2S64}));
// Merge/Unmerge
for (unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) {
Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=365482&r1=365481&r2=365482&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp Tue Jul 9 07:02:20 2019
@@ -1573,27 +1573,43 @@ ArrayRef<int16_t> SIRegisterInfo::getReg
}
}
- assert(EltSize == 16 && "unhandled register spill split size");
+ if (EltSize == 16) {
+ static const int16_t Sub0_15_128[] = {
+ AMDGPU::sub0_sub1_sub2_sub3,
+ AMDGPU::sub4_sub5_sub6_sub7,
+ AMDGPU::sub8_sub9_sub10_sub11,
+ AMDGPU::sub12_sub13_sub14_sub15
+ };
+
+ static const int16_t Sub0_7_128[] = {
+ AMDGPU::sub0_sub1_sub2_sub3,
+ AMDGPU::sub4_sub5_sub6_sub7
+ };
+
+ switch (AMDGPU::getRegBitWidth(*RC->MC)) {
+ case 128:
+ return {};
+ case 256:
+ return makeArrayRef(Sub0_7_128);
+ case 512:
+ return makeArrayRef(Sub0_15_128);
+ default:
+ llvm_unreachable("unhandled register size");
+ }
+ }
- static const int16_t Sub0_15_128[] = {
- AMDGPU::sub0_sub1_sub2_sub3,
- AMDGPU::sub4_sub5_sub6_sub7,
- AMDGPU::sub8_sub9_sub10_sub11,
- AMDGPU::sub12_sub13_sub14_sub15
- };
+ assert(EltSize == 32 && "unhandled elt size");
- static const int16_t Sub0_7_128[] = {
- AMDGPU::sub0_sub1_sub2_sub3,
- AMDGPU::sub4_sub5_sub6_sub7
+ static const int16_t Sub0_15_256[] = {
+ AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7,
+ AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15
};
switch (AMDGPU::getRegBitWidth(*RC->MC)) {
- case 128:
- return {};
case 256:
- return makeArrayRef(Sub0_7_128);
+ return {};
case 512:
- return makeArrayRef(Sub0_15_128);
+ return makeArrayRef(Sub0_15_256);
default:
llvm_unreachable("unhandled register size");
}
@@ -1727,8 +1743,7 @@ SIRegisterInfo::getRegClassForSizeOnBank
if (Size < 32)
return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VGPR_32RegClass :
&AMDGPU::SReg_32_XM0RegClass;
- assert(Size < 512 && "unimplemented");
- return getRegClassForSizeOnBank(PowerOf2Ceil(Size), RB, MRI);
+ return nullptr;
}
}
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir?rev=365482&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir Tue Jul 9 07:02:20 2019
@@ -0,0 +1,738 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -o - %s 2> %t | FileCheck -check-prefix=GCN %s
+# RUN: FileCheck -check-prefix=ERR %s < %t
+
+# ERR-NOT: remark:
+# ERR: remark: <unknown>:0:0: cannot select: %3:sgpr(<12 x s16>) = G_CONCAT_VECTORS %0:sgpr(<4 x s16>), %1:sgpr(<4 x s16>), %2:sgpr(<4 x s16>) (in function: test_concat_vectors_s_v12s16_s_v4s16_s_v4s16_s_v4s16)
+# ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(<12 x s16>) = G_CONCAT_VECTORS %0:vgpr(<4 x s16>), %1:vgpr(<4 x s16>), %2:vgpr(<4 x s16>) (in function: test_concat_vectors_v_v12s16_v_v4s16_v_v4s16_v_v4s16)
+# ERR-NEXT: remark: <unknown>:0:0: instruction is not legal: %2:sgpr(<6 x s64>) = G_CONCAT_VECTORS %0:sgpr(<3 x s64>), %1:sgpr(<3 x s64>) (in function: test_concat_vectors_s_v6s64_s_v3s64_s_v3s64)
+# ERR-NEXT: remark: <unknown>:0:0: instruction is not legal: %2:sgpr(<8 x s64>) = G_CONCAT_VECTORS %0:sgpr(<4 x s64>), %1:sgpr(<4 x s64>) (in function: test_concat_vectors_s_v8s64_s_v4s64_s_v4s64)
+# ERR-NEXT: remark: <unknown>:0:0: instruction is not legal: %2:sgpr(<4 x p1>) = G_CONCAT_VECTORS %0:sgpr(<2 x p1>), %1:sgpr(<2 x p1>) (in function: test_concat_vectors_s_v4p1_s_v2p1_s_v2p1)
+# ERR-NEXT: remark: <unknown>:0:0: instruction is not legal: %4:sgpr(<8 x p3>) = G_CONCAT_VECTORS %0:sgpr(<2 x p3>), %1:sgpr(<2 x p3>), %2:sgpr(<2 x p3>), %3:sgpr(<2 x p3>) (in function: test_concat_vectors_s_v8p3_s_v2p3_s_v2p3_v2p3_s_v2p3)
+# ERR-NOT: remark:
+
+---
+name: test_concat_vectors_v_v4s16_v_v2s16_v_v2s16
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; GCN-LABEL: name: test_concat_vectors_v_v4s16_v_v2s16_v_v2s16
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GCN: $vgpr0_vgpr1 = COPY [[REG_SEQUENCE]]
+ %0:vgpr(<2 x s16>) = COPY $vgpr0
+ %1:vgpr(<2 x s16>) = COPY $vgpr1
+ %2:vgpr(<4 x s16>) = G_CONCAT_VECTORS %0, %1
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: test_concat_vectors_v_v4s16_s_v2s16_v_v2s16
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0
+
+ ; GCN-LABEL: name: test_concat_vectors_v_v4s16_s_v2s16_v_v2s16
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GCN: $vgpr0_vgpr1 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(<2 x s16>) = COPY $sgpr0
+ %1:vgpr(<2 x s16>) = COPY $vgpr1
+ %2:vgpr(<4 x s16>) = G_CONCAT_VECTORS %0, %1
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: test_concat_vectors_v_v4s16_v_v2s16_s_v2s16
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0
+
+ ; GCN-LABEL: name: test_concat_vectors_v_v4s16_v_v2s16_s_v2s16
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GCN: $vgpr0_vgpr1 = COPY [[REG_SEQUENCE]]
+ %0:vgpr(<2 x s16>) = COPY $vgpr0
+ %1:sgpr(<2 x s16>) = COPY $sgpr0
+ %2:vgpr(<4 x s16>) = G_CONCAT_VECTORS %0, %1
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: test_concat_vectors_s_v4s16_s_v2s16_s_v2s16
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+
+ ; GCN-LABEL: name: test_concat_vectors_s_v4s16_s_v2s16_s_v2s16
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GCN: $sgpr0_sgpr1 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(<2 x s16>) = COPY $sgpr0
+ %1:sgpr(<2 x s16>) = COPY $sgpr1
+ %2:sgpr(<4 x s16>) = G_CONCAT_VECTORS %0, %1
+ $sgpr0_sgpr1 = COPY %2
+...
+
+---
+name: test_concat_vectors_s_s96_s_v2s16_s_v2s16_s_v2s16
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr2
+
+ ; GCN-LABEL: name: test_concat_vectors_s_s96_s_v2s16_s_v2s16_s_v2s16
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+ ; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2
+ ; GCN: $sgpr0_sgpr1_sgpr2 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(<2 x s16>) = COPY $sgpr0
+ %1:sgpr(<2 x s16>) = COPY $sgpr1
+ %2:sgpr(<2 x s16>) = COPY $sgpr2
+ %3:sgpr(<6 x s16>) = G_CONCAT_VECTORS %0, %1, %2
+ $sgpr0_sgpr1_sgpr2 = COPY %3
+...
+
+---
+name: test_concat_vectors_v_s96_v_v2s16_v_v2s16_v_v2s16
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2
+
+ ; GCN-LABEL: name: test_concat_vectors_v_s96_v_v2s16_v_v2s16_v_v2s16
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2
+ ; GCN: $vgpr0_vgpr1_vgpr2 = COPY [[REG_SEQUENCE]]
+ %0:vgpr(<2 x s16>) = COPY $vgpr0
+ %1:vgpr(<2 x s16>) = COPY $vgpr1
+ %2:vgpr(<2 x s16>) = COPY $vgpr2
+ %3:vgpr(<6 x s16>) = G_CONCAT_VECTORS %0, %1, %2
+ $vgpr0_vgpr1_vgpr2 = COPY %3
+...
+
+---
+name: test_concat_vectors_s_v8s16_s_v2s16_s_v2s16_s_v2s16_s_v2s16
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
+
+ ; GCN-LABEL: name: test_concat_vectors_s_v8s16_s_v2s16_s_v2s16_s_v2s16_s_v2s16
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+ ; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2
+ ; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(<2 x s16>) = COPY $sgpr0
+ %1:sgpr(<2 x s16>) = COPY $sgpr1
+ %2:sgpr(<2 x s16>) = COPY $sgpr2
+ %3:sgpr(<2 x s16>) = COPY $sgpr3
+ %4:sgpr(<8 x s16>) = G_CONCAT_VECTORS %0, %1, %2, %3
+ $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %4
+...
+
+---
+name: test_concat_vectors_v_v8s16_v_v2s16_v_v2s16_v_v2s16
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+
+ ; GCN-LABEL: name: test_concat_vectors_v_v8s16_v_v2s16_v_v2s16_v_v2s16
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+ ; GCN: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[REG_SEQUENCE]]
+ %0:vgpr(<2 x s16>) = COPY $vgpr0
+ %1:vgpr(<2 x s16>) = COPY $vgpr1
+ %2:vgpr(<2 x s16>) = COPY $vgpr2
+ %3:vgpr(<2 x s16>) = COPY $vgpr3
+ %4:vgpr(<8 x s16>) = G_CONCAT_VECTORS %0, %1, %2, %3
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %4
+...
+
+---
+name: test_concat_vectors_s_v8s16_s_v4s16_s_v4s16
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+
+ ; GCN-LABEL: name: test_concat_vectors_s_v8s16_s_v4s16_s_v4s16
+ ; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
+ %1:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
+ %2:sgpr(<8 x s16>) = G_CONCAT_VECTORS %0, %1
+ $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %2
+...
+
+---
+name: test_concat_vectors_v_v8s16_v_v4s16_v_v4s16
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; GCN-LABEL: name: test_concat_vectors_v_v8s16_v_v4s16_v_v4s16
+ ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
+ ; GCN: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[REG_SEQUENCE]]
+ %0:vgpr(<4 x s16>) = COPY $vgpr0_vgpr1
+ %1:vgpr(<4 x s16>) = COPY $vgpr2_vgpr3
+ %2:vgpr(<8 x s16>) = G_CONCAT_VECTORS %0, %1
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
+...
+
+---
+name: test_concat_vectors_s_s160_s_v2s16_s_v2s16_s_v2s16_s_v2s16_s_v2s16
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4
+
+ ; GCN-LABEL: name: test_concat_vectors_s_s160_s_v2s16_s_v2s16_s_v2s16_s_v2s16_s_v2s16
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+ ; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2
+ ; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3
+ ; GCN: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_160 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3, [[COPY4]], %subreg.sub4
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(<2 x s16>) = COPY $sgpr0
+ %1:sgpr(<2 x s16>) = COPY $sgpr1
+ %2:sgpr(<2 x s16>) = COPY $sgpr2
+ %3:sgpr(<2 x s16>) = COPY $sgpr3
+ %4:sgpr(<2 x s16>) = COPY $sgpr4
+ %5:sgpr(<10 x s16>) = G_CONCAT_VECTORS %0, %1, %2, %3, %4
+ $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4 = COPY %5
+...
+
+---
+name: test_concat_vectors_v_s160_v_v2s16_v_v2s16_v_v2s16_v_v2s16_v_v2s16
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+
+ ; GCN-LABEL: name: test_concat_vectors_v_s160_v_v2s16_v_v2s16_v_v2s16_v_v2s16_v_v2s16
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GCN: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_160 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3, [[COPY4]], %subreg.sub4
+ ; GCN: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = COPY [[REG_SEQUENCE]]
+ %0:vgpr(<2 x s16>) = COPY $vgpr0
+ %1:vgpr(<2 x s16>) = COPY $vgpr1
+ %2:vgpr(<2 x s16>) = COPY $vgpr2
+ %3:vgpr(<2 x s16>) = COPY $vgpr3
+ %4:vgpr(<2 x s16>) = COPY $vgpr4
+ %5:vgpr(<10 x s16>) = G_CONCAT_VECTORS %0, %1, %2, %3, %4
+ $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = COPY %5
+...
+
+---
+name: test_concat_vectors_s_v12s16_s_v4s16_s_v4s16_s_v4s16
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5
+
+ ; GCN-LABEL: name: test_concat_vectors_s_v12s16_s_v4s16_s_v4s16_s_v4s16
+ ; GCN: [[COPY:%[0-9]+]]:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
+ ; GCN: [[COPY1:%[0-9]+]]:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
+ ; GCN: [[COPY2:%[0-9]+]]:sgpr(<4 x s16>) = COPY $sgpr4_sgpr5
+ ; GCN: [[CONCAT_VECTORS:%[0-9]+]]:sgpr(<12 x s16>) = G_CONCAT_VECTORS [[COPY]](<4 x s16>), [[COPY1]](<4 x s16>), [[COPY2]](<4 x s16>)
+ ; GCN: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<12 x s16>)
+ %0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
+ %1:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
+ %2:sgpr(<4 x s16>) = COPY $sgpr4_sgpr5
+ %3:sgpr(<12 x s16>) = G_CONCAT_VECTORS %0, %1, %2
+ S_ENDPGM 0, implicit %3
+...
+
+---
+name: test_concat_vectors_v_v12s16_v_v4s16_v_v4s16_v_v4s16
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+
+ ; GCN-LABEL: name: test_concat_vectors_v_v12s16_v_v4s16_v_v4s16_v_v4s16
+ ; GCN: [[COPY:%[0-9]+]]:vgpr(<4 x s16>) = COPY $vgpr0_vgpr1
+ ; GCN: [[COPY1:%[0-9]+]]:vgpr(<4 x s16>) = COPY $vgpr2_vgpr3
+ ; GCN: [[COPY2:%[0-9]+]]:vgpr(<4 x s16>) = COPY $vgpr4_vgpr5
+ ; GCN: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<12 x s16>) = G_CONCAT_VECTORS [[COPY]](<4 x s16>), [[COPY1]](<4 x s16>), [[COPY2]](<4 x s16>)
+ ; GCN: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<12 x s16>)
+ %0:vgpr(<4 x s16>) = COPY $vgpr0_vgpr1
+ %1:vgpr(<4 x s16>) = COPY $vgpr2_vgpr3
+ %2:vgpr(<4 x s16>) = COPY $vgpr4_vgpr5
+ %3:vgpr(<12 x s16>) = G_CONCAT_VECTORS %0, %1, %2
+ S_ENDPGM 0, implicit %3
+...
+
+---
+name: test_concat_vectors_s_v16s16_s_v4s16_s_v4s16_s_v4s16_s_v4s16
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6_sgpr7
+
+ ; GCN-LABEL: name: test_concat_vectors_s_v16s16_s_v4s16_s_v4s16_s_v4s16_s_v4s16
+ ; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+ ; GCN: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5
+ ; GCN: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY $sgpr6_sgpr7
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_256 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3, [[COPY2]], %subreg.sub4_sub5, [[COPY3]], %subreg.sub6_sub7
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
+ %1:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
+ %2:sgpr(<4 x s16>) = COPY $sgpr4_sgpr5
+ %3:sgpr(<4 x s16>) = COPY $sgpr6_sgpr7
+ %4:sgpr(<16 x s16>) = G_CONCAT_VECTORS %0, %1, %2, %3
+ $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY %4
+...
+
+---
+name: test_concat_vectors_s_v12s16_s_v8s16_s_v8s16
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7
+
+ ; GCN-LABEL: name: test_concat_vectors_s_v12s16_s_v8s16_s_v8s16
+ ; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_256 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1_sub2_sub3, [[COPY1]], %subreg.sub4_sub5_sub6_sub7
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(<8 x s16>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ %1:sgpr(<8 x s16>) = COPY $sgpr4_sgpr5_sgpr6_sgpr7
+ %2:sgpr(<16 x s16>) = G_CONCAT_VECTORS %0, %1
+ $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY %2
+...
+
+---
+name: test_concat_vectors_s_v32s16_s_v12s16_s_v12s16
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+
+ ; GCN-LABEL: name: test_concat_vectors_s_v32s16_s_v12s16_s_v12s16
+ ; GCN: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_256 = COPY $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_512 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7, [[COPY1]], %subreg.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(<16 x s16>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7,
+ %1:sgpr(<16 x s16>) = COPY $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ %4:sgpr(<32 x s16>) = G_CONCAT_VECTORS %0, %1
+ $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %4
+...
+
+---
+name: test_concat_vectors_s_v32s16_s_v4s16_s_v4s16_s_v4s16_s_v4s16_s_v4s16_s_v4s16_s_v4s16_s_v4s16
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15
+
+ ; GCN-LABEL: name: test_concat_vectors_s_v32s16_s_v4s16_s_v4s16_s_v4s16_s_v4s16_s_v4s16_s_v4s16_s_v4s16_s_v4s16
+ ; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+ ; GCN: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5
+ ; GCN: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY $sgpr6_sgpr7
+ ; GCN: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr8_sgpr9
+ ; GCN: [[COPY5:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11
+ ; GCN: [[COPY6:%[0-9]+]]:sreg_64_xexec = COPY $sgpr12_sgpr13
+ ; GCN: [[COPY7:%[0-9]+]]:sreg_64_xexec = COPY $sgpr14_sgpr15
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_512 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3, [[COPY2]], %subreg.sub4_sub5, [[COPY3]], %subreg.sub6_sub7, [[COPY4]], %subreg.sub8_sub9, [[COPY5]], %subreg.sub10_sub11, [[COPY6]], %subreg.sub12_sub13, [[COPY7]], %subreg.sub14_sub15
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
+ %1:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
+ %2:sgpr(<4 x s16>) = COPY $sgpr4_sgpr5
+ %3:sgpr(<4 x s16>) = COPY $sgpr6_sgpr7
+ %4:sgpr(<4 x s16>) = COPY $sgpr8_sgpr9
+ %5:sgpr(<4 x s16>) = COPY $sgpr10_sgpr11
+ %6:sgpr(<4 x s16>) = COPY $sgpr12_sgpr13
+ %7:sgpr(<4 x s16>) = COPY $sgpr14_sgpr15
+ %8:sgpr(<32 x s16>) = G_CONCAT_VECTORS %0, %1, %2, %3, %4, %5, %6, %7
+ $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %8
+...
+
+---
+name: test_concat_vectors_v_v512_v_v64_v_v64_v_v64_v_v64_v_v64_v_v64_v_v64_v_v64
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7, $vgpr8_vgpr9, $vgpr10_vgpr11, $vgpr12_vgpr13, $vgpr14_vgpr15
+
+ ; GCN-LABEL: name: test_concat_vectors_v_v512_v_v64_v_v64_v_v64_v_v64_v_v64_v_v64_v_v64_v_v64
+ ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
+ ; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr6_vgpr7
+ ; GCN: [[COPY4:%[0-9]+]]:vreg_64 = COPY $vgpr8_vgpr9
+ ; GCN: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
+ ; GCN: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
+ ; GCN: [[COPY7:%[0-9]+]]:vreg_64 = COPY $vgpr14_vgpr15
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3, [[COPY2]], %subreg.sub4_sub5, [[COPY3]], %subreg.sub6_sub7, [[COPY4]], %subreg.sub8_sub9, [[COPY5]], %subreg.sub10_sub11, [[COPY6]], %subreg.sub12_sub13, [[COPY7]], %subreg.sub14_sub15
+ ; GCN: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[REG_SEQUENCE]]
+ %0:vgpr(<4 x s16>) = COPY $vgpr0_vgpr1
+ %1:vgpr(<4 x s16>) = COPY $vgpr2_vgpr3
+ %2:vgpr(<4 x s16>) = COPY $vgpr4_vgpr5
+ %3:vgpr(<4 x s16>) = COPY $vgpr6_vgpr7
+ %4:vgpr(<4 x s16>) = COPY $vgpr8_vgpr9
+ %5:vgpr(<4 x s16>) = COPY $vgpr10_vgpr11
+ %6:vgpr(<4 x s16>) = COPY $vgpr12_vgpr13
+ %7:vgpr(<4 x s16>) = COPY $vgpr14_vgpr15
+ %8:vgpr(<32 x s16>) = G_CONCAT_VECTORS %0, %1, %2, %3, %4, %5, %6, %7
+ $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY %8
+...
+
+
+
+
+
+
+---
+name: test_concat_vectors_s_v4s32_s_v2s32_s_v2s32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+
+ ; GCN-LABEL: name: test_concat_vectors_s_v4s32_s_v2s32_s_v2s32
+ ; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
+ %1:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
+ %4:sgpr(<4 x s32>) = G_CONCAT_VECTORS %0, %1
+ $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %4
+...
+
+---
+name: test_concat_vectors_v_v4s32_v_v2s32_v_v2s32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; GCN-LABEL: name: test_concat_vectors_v_v4s32_v_v2s32_v_v2s32
+ ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
+ ; GCN: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[REG_SEQUENCE]]
+ %0:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1
+ %1:vgpr(<2 x s32>) = COPY $vgpr2_vgpr3
+ %2:vgpr(<4 x s32>) = G_CONCAT_VECTORS %0, %1
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
+...
+
+---
+name: test_concat_vectors_s_v8s32_s_v2s32_s_v2s32_s_v2s32_s_v2s32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6_sgpr7
+
+ ; GCN-LABEL: name: test_concat_vectors_s_v8s32_s_v2s32_s_v2s32_s_v2s32_s_v2s32
+ ; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+ ; GCN: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5
+ ; GCN: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY $sgpr6_sgpr7
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_256 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3, [[COPY2]], %subreg.sub4_sub5, [[COPY3]], %subreg.sub6_sub7
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
+ %1:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
+ %2:sgpr(<2 x s32>) = COPY $sgpr4_sgpr5
+ %3:sgpr(<2 x s32>) = COPY $sgpr6_sgpr7
+ %4:sgpr(<8 x s32>) = G_CONCAT_VECTORS %0, %1, %2, %3
+ $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY %4
+...
+
+---
+
+name: test_concat_vectors_s_v8s32_s_v4s32_s_v4s32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7
+
+ ; GCN-LABEL: name: test_concat_vectors_s_v8s32_s_v4s32_s_v4s32
+ ; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_256 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1_sub2_sub3, [[COPY1]], %subreg.sub4_sub5_sub6_sub7
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ %1:sgpr(<4 x s32>) = COPY $sgpr4_sgpr5_sgpr6_sgpr7
+ %2:sgpr(<8 x s32>) = G_CONCAT_VECTORS %0, %1
+ $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY %2
+...
+
+---
+name: test_concat_vectors_s_v16s32_s_v8s32_s_v8s32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+
+ ; GCN-LABEL: name: test_concat_vectors_s_v16s32_s_v8s32_s_v8s32
+ ; GCN: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_256 = COPY $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_512 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7, [[COPY1]], %subreg.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7,
+ %1:sgpr(<8 x s32>) = COPY $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ %4:sgpr(<16 x s32>) = G_CONCAT_VECTORS %0, %1
+ $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %4
+...
+
+---
+name: test_concat_vectors_v_v16s32_v_v2s32_v_v2s32_v_v2s32_v_v2s32_v_v2s32_v_v2s32_v_v2s32_v_v2s32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7, $vgpr8_vgpr9, $vgpr10_vgpr11, $vgpr12_vgpr13, $vgpr14_vgpr15
+
+ ; GCN-LABEL: name: test_concat_vectors_v_v16s32_v_v2s32_v_v2s32_v_v2s32_v_v2s32_v_v2s32_v_v2s32_v_v2s32_v_v2s32
+ ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
+ ; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr6_vgpr7
+ ; GCN: [[COPY4:%[0-9]+]]:vreg_64 = COPY $vgpr8_vgpr9
+ ; GCN: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
+ ; GCN: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
+ ; GCN: [[COPY7:%[0-9]+]]:vreg_64 = COPY $vgpr14_vgpr15
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3, [[COPY2]], %subreg.sub4_sub5, [[COPY3]], %subreg.sub6_sub7, [[COPY4]], %subreg.sub8_sub9, [[COPY5]], %subreg.sub10_sub11, [[COPY6]], %subreg.sub12_sub13, [[COPY7]], %subreg.sub14_sub15
+ ; GCN: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[REG_SEQUENCE]]
+ %0:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1
+ %1:vgpr(<2 x s32>) = COPY $vgpr2_vgpr3
+ %2:vgpr(<2 x s32>) = COPY $vgpr4_vgpr5
+ %3:vgpr(<2 x s32>) = COPY $vgpr6_vgpr7
+ %4:vgpr(<2 x s32>) = COPY $vgpr8_vgpr9
+ %5:vgpr(<2 x s32>) = COPY $vgpr10_vgpr11
+ %6:vgpr(<2 x s32>) = COPY $vgpr12_vgpr13
+ %7:vgpr(<2 x s32>) = COPY $vgpr14_vgpr15
+ %8:vgpr(<16 x s32>) = G_CONCAT_VECTORS %0, %1, %2, %3, %4, %5, %6, %7
+ $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY %8
+...
+
+---
+name: test_concat_vectors_s_v4s64_s_v2s64_s_v2s64
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7
+
+ ; GCN-LABEL: name: test_concat_vectors_s_v4s64_s_v2s64_s_v2s64
+ ; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_256 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1_sub2_sub3, [[COPY1]], %subreg.sub4_sub5_sub6_sub7
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(<2 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ %1:sgpr(<2 x s64>) = COPY $sgpr4_sgpr5_sgpr6_sgpr7
+ %3:sgpr(<4 x s64>) = G_CONCAT_VECTORS %0, %1
+ $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY %3
+...
+
+---
+name: test_concat_vectors_s_v6s64_s_v3s64_s_v3s64
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+
+ ; GCN-LABEL: name: test_concat_vectors_s_v6s64_s_v3s64_s_v3s64
+ ; GCN: [[DEF:%[0-9]+]]:sgpr(<3 x s64>) = G_IMPLICIT_DEF
+ ; GCN: [[DEF1:%[0-9]+]]:sgpr(<3 x s64>) = G_IMPLICIT_DEF
+ ; GCN: [[CONCAT_VECTORS:%[0-9]+]]:sgpr(<6 x s64>) = G_CONCAT_VECTORS [[DEF]](<3 x s64>), [[DEF1]](<3 x s64>)
+ ; GCN: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<6 x s64>)
+ %0:sgpr(<3 x s64>) = G_IMPLICIT_DEF
+ %1:sgpr(<3 x s64>) = G_IMPLICIT_DEF
+ %2:sgpr(<6 x s64>) = G_CONCAT_VECTORS %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: test_concat_vectors_s_v8s64_s_v4s64_s_v4s64
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+
+ ; GCN-LABEL: name: test_concat_vectors_s_v8s64_s_v4s64_s_v4s64
+ ; GCN: [[COPY:%[0-9]+]]:sgpr(<4 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; GCN: [[COPY1:%[0-9]+]]:sgpr(<4 x s64>) = COPY $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; GCN: [[CONCAT_VECTORS:%[0-9]+]]:sgpr(<8 x s64>) = G_CONCAT_VECTORS [[COPY]](<4 x s64>), [[COPY1]](<4 x s64>)
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY [[CONCAT_VECTORS]](<8 x s64>)
+ %0:sgpr(<4 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7,
+ %1:sgpr(<4 x s64>) = COPY $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ %4:sgpr(<8 x s64>) = G_CONCAT_VECTORS %0, %1
+ $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %4
+...
+
+---
+name: test_concat_vectors_s_v8s64_s_v2s64_s_v2s64_s_v2s64_s_v2s64
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr12_sgpr13_sgpr14_sgpr15
+
+ ; GCN-LABEL: name: test_concat_vectors_s_v8s64_s_v2s64_s_v2s64_s_v2s64_s_v2s64
+ ; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
+ ; GCN: [[COPY2:%[0-9]+]]:sreg_128 = COPY $sgpr8_sgpr9_sgpr10_sgpr11
+ ; GCN: [[COPY3:%[0-9]+]]:sreg_128 = COPY $sgpr12_sgpr13_sgpr14_sgpr15
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_512 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1_sub2_sub3, [[COPY1]], %subreg.sub4_sub5_sub6_sub7, [[COPY2]], %subreg.sub8_sub9_sub10_sub11, [[COPY3]], %subreg.sub12_sub13_sub14_sub15
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(<2 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ %1:sgpr(<2 x s64>) = COPY $sgpr4_sgpr5_sgpr6_sgpr7
+ %2:sgpr(<2 x s64>) = COPY $sgpr8_sgpr9_sgpr10_sgpr11
+ %3:sgpr(<2 x s64>) = COPY $sgpr12_sgpr13_sgpr14_sgpr15
+ %4:sgpr(<8 x s64>) = G_CONCAT_VECTORS %0, %1, %2, %3
+ $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %4
+...
+
+---
+name: test_concat_vectors_s_v4p1_s_v2p1_s_v2p1
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7
+
+ ; GCN-LABEL: name: test_concat_vectors_s_v4p1_s_v2p1_s_v2p1
+ ; GCN: [[COPY:%[0-9]+]]:sgpr(<2 x p1>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GCN: [[COPY1:%[0-9]+]]:sgpr(<2 x p1>) = COPY $sgpr4_sgpr5_sgpr6_sgpr7
+ ; GCN: [[CONCAT_VECTORS:%[0-9]+]]:sgpr(<4 x p1>) = G_CONCAT_VECTORS [[COPY]](<2 x p1>), [[COPY1]](<2 x p1>)
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[CONCAT_VECTORS]](<4 x p1>)
+ %0:sgpr(<2 x p1>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ %1:sgpr(<2 x p1>) = COPY $sgpr4_sgpr5_sgpr6_sgpr7
+ %3:sgpr(<4 x p1>) = G_CONCAT_VECTORS %0, %1
+ $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY %3
+...
+
+---
+name: test_concat_vectors_s_v4p3_s_v2p3_s_v2p3
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+
+ ; GCN-LABEL: name: test_concat_vectors_s_v4p3_s_v2p3_s_v2p3
+ ; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(<2 x p3>) = COPY $sgpr0_sgpr1
+ %1:sgpr(<2 x p3>) = COPY $sgpr2_sgpr3
+ %2:sgpr(<4 x p3>) = G_CONCAT_VECTORS %0, %1
+ $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %2
+...
+
+---
+name: test_concat_vectors_s_v8p3_s_v2p3_s_v2p3_v2p3_s_v2p3
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6_sgpr7
+
+ ; GCN-LABEL: name: test_concat_vectors_s_v8p3_s_v2p3_s_v2p3_v2p3_s_v2p3
+ ; GCN: [[COPY:%[0-9]+]]:sgpr(<2 x p3>) = COPY $sgpr0_sgpr1
+ ; GCN: [[COPY1:%[0-9]+]]:sgpr(<2 x p3>) = COPY $sgpr2_sgpr3
+ ; GCN: [[COPY2:%[0-9]+]]:sgpr(<2 x p3>) = COPY $sgpr4_sgpr5
+ ; GCN: [[COPY3:%[0-9]+]]:sgpr(<2 x p3>) = COPY $sgpr6_sgpr7
+ ; GCN: [[CONCAT_VECTORS:%[0-9]+]]:sgpr(<8 x p3>) = G_CONCAT_VECTORS [[COPY]](<2 x p3>), [[COPY1]](<2 x p3>), [[COPY2]](<2 x p3>), [[COPY3]](<2 x p3>)
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[CONCAT_VECTORS]](<8 x p3>)
+ %0:sgpr(<2 x p3>) = COPY $sgpr0_sgpr1
+ %1:sgpr(<2 x p3>) = COPY $sgpr2_sgpr3
+ %2:sgpr(<2 x p3>) = COPY $sgpr4_sgpr5
+ %3:sgpr(<2 x p3>) = COPY $sgpr6_sgpr7
+ %4:sgpr(<8 x p3>) = G_CONCAT_VECTORS %0, %1, %2, %3
+ $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY %4
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir?rev=365482&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir Tue Jul 9 07:02:20 2019
@@ -0,0 +1,565 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' -o - %s 2> %t | FileCheck -check-prefix=GCN %s
+# RUN: FileCheck -check-prefix=ERR %s < %t
+
+
+# ERR-NOT: remark:
+# ERR: remark: <unknown>:0:0: cannot select: %3:sgpr(s192) = G_MERGE_VALUES %0:sgpr(s64), %1:sgpr(s64), %2:sgpr(s64) (in function: test_merge_values_s_s192_s_s64_s_s64_s_s64)
+# ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s192) = G_MERGE_VALUES %0:vgpr(s64), %1:vgpr(s64), %2:vgpr(s64) (in function: test_merge_values_v_s192_v_s64_v_s64_v_s64)
+# ERR-NOT: remark:
+
+---
+name: test_merge_values_v_s64_v_s32_v_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; GCN-LABEL: name: test_merge_values_v_s64_v_s32_v_s32
+ ; GCN: liveins: $vgpr0, $vgpr1
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s64) = G_MERGE_VALUES %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: test_merge_values_v_s64_s_s32_v_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0
+
+ ; GCN-LABEL: name: test_merge_values_v_s64_s_s32_v_s32
+ ; GCN: liveins: $sgpr0, $vgpr0
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:vgpr(s32) = COPY $vgpr0
+ %2:vgpr(s64) = G_MERGE_VALUES %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: test_merge_values_v_s64_v_s32_s_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0
+
+ ; GCN-LABEL: name: test_merge_values_v_s64_v_s32_s_s32
+ ; GCN: liveins: $sgpr0, $vgpr0
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:sgpr(s32) = COPY $sgpr0
+ %2:vgpr(s64) = G_MERGE_VALUES %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: test_merge_values_s_s64_s_s32_s_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+
+ ; GCN-LABEL: name: test_merge_values_s_s64_s_s32_s_s32
+ ; GCN: liveins: $sgpr0, $sgpr1
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:sgpr(s32) = COPY $sgpr1
+ %2:sgpr(s64) = G_MERGE_VALUES %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: test_merge_values_s_s64_undef_s_s32_s_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; GCN-LABEL: name: test_merge_values_s_s64_undef_s_s32_s_s32
+ ; GCN: liveins: $sgpr0
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE undef %2:sreg_32_xm0, %subreg.sub0, [[COPY]], %subreg.sub1
+ ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %1:sgpr(s32) = COPY $sgpr0
+ %2:sgpr(s64) = G_MERGE_VALUES undef %0:sgpr(s32), %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: test_merge_values_s_s64_s_s32_undef_s_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; GCN-LABEL: name: test_merge_values_s_s64_s_s32_undef_s_s32
+ ; GCN: liveins: $sgpr0
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[COPY]], %subreg.sub0, undef %2:sreg_32_xm0, %subreg.sub1
+ ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %2:sgpr(s64) = G_MERGE_VALUES %0, undef %1:sgpr(s32),
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: test_merge_values_s_s96_s_s32_s_s32_s_s32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr2
+
+ ; GCN-LABEL: name: test_merge_values_s_s96_s_s32_s_s32_s_s32
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+ ; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2
+ ; GCN: $sgpr0_sgpr1_sgpr2 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:sgpr(s32) = COPY $sgpr1
+ %2:sgpr(s32) = COPY $sgpr2
+ %3:sgpr(s96) = G_MERGE_VALUES %0, %1, %2
+ $sgpr0_sgpr1_sgpr2 = COPY %3
+...
+
+---
+name: test_merge_values_v_s96_v_s32_v_s32_v_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2
+
+ ; GCN-LABEL: name: test_merge_values_v_s96_v_s32_v_s32_v_s32
+ ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2
+ ; GCN: $vgpr0_vgpr1_vgpr2 = COPY [[REG_SEQUENCE]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = COPY $vgpr2
+ %3:vgpr(s96) = G_MERGE_VALUES %0, %1, %2
+ $vgpr0_vgpr1_vgpr2 = COPY %3
+...
+
+---
+name: test_merge_values_s_s128_s_s32_s_s32_s_s32_s_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
+
+ ; GCN-LABEL: name: test_merge_values_s_s128_s_s32_s_s32_s_s32_s_s32
+ ; GCN: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+ ; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2
+ ; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:sgpr(s32) = COPY $sgpr1
+ %2:sgpr(s32) = COPY $sgpr2
+ %3:sgpr(s32) = COPY $sgpr3
+ %4:sgpr(s128) = G_MERGE_VALUES %0, %1, %2, %3
+ $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %4
+...
+
+---
+name: test_merge_values_v_s128_v_s32_v_s32_v_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+
+ ; GCN-LABEL: name: test_merge_values_v_s128_v_s32_v_s32_v_s32
+ ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+ ; GCN: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[REG_SEQUENCE]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = COPY $vgpr2
+ %3:vgpr(s32) = COPY $vgpr3
+ %4:vgpr(s128) = G_MERGE_VALUES %0, %1, %2, %3
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %4
+...
+
+---
+name: test_merge_values_s_s128_s_s64_s_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+
+ ; GCN-LABEL: name: test_merge_values_s_s128_s_s64_s_s64
+ ; GCN: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+ ; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(s64) = COPY $sgpr0_sgpr1
+ %1:sgpr(s64) = COPY $sgpr2_sgpr3
+ %4:sgpr(s128) = G_MERGE_VALUES %0, %1
+ $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %4
+...
+
+---
+name: test_merge_values_v_s128_v_s64_v_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; GCN-LABEL: name: test_merge_values_v_s128_v_s64_v_s64
+ ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
+ ; GCN: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[REG_SEQUENCE]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vgpr(s128) = G_MERGE_VALUES %0, %1
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
+...
+
+---
+name: test_merge_values_s_s160_s_s32_s_s32_s_s32_s_s32_s_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4
+
+ ; GCN-LABEL: name: test_merge_values_s_s160_s_s32_s_s32_s_s32_s_s32_s_s32
+ ; GCN: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+ ; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2
+ ; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3
+ ; GCN: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_160 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3, [[COPY4]], %subreg.sub4
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:sgpr(s32) = COPY $sgpr1
+ %2:sgpr(s32) = COPY $sgpr2
+ %3:sgpr(s32) = COPY $sgpr3
+ %4:sgpr(s32) = COPY $sgpr4
+ %5:sgpr(s160) = G_MERGE_VALUES %0, %1, %2, %3, %4
+ $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4 = COPY %5
+...
+
+---
+name: test_merge_values_v_s160_v_s32_v_s32_v_s32_v_s32_v_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+
+ ; GCN-LABEL: name: test_merge_values_v_s160_v_s32_v_s32_v_s32_v_s32_v_s32
+ ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GCN: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_160 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3, [[COPY4]], %subreg.sub4
+ ; GCN: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = COPY [[REG_SEQUENCE]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = COPY $vgpr2
+ %3:vgpr(s32) = COPY $vgpr3
+ %4:vgpr(s32) = COPY $vgpr4
+ %5:vgpr(s160) = G_MERGE_VALUES %0, %1, %2, %3, %4
+ $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = COPY %5
+...
+
+---
+name: test_merge_values_s_s192_s_s64_s_s64_s_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5
+
+ ; GCN-LABEL: name: test_merge_values_s_s192_s_s64_s_s64_s_s64
+ ; GCN: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5
+ ; GCN: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; GCN: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
+ ; GCN: [[COPY2:%[0-9]+]]:sgpr(s64) = COPY $sgpr4_sgpr5
+ ; GCN: [[MV:%[0-9]+]]:sgpr(s192) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64)
+ ; GCN: S_ENDPGM 0, implicit [[MV]](s192)
+ %0:sgpr(s64) = COPY $sgpr0_sgpr1
+ %1:sgpr(s64) = COPY $sgpr2_sgpr3
+ %2:sgpr(s64) = COPY $sgpr4_sgpr5
+ %3:sgpr(s192) = G_MERGE_VALUES %0, %1, %2
+ S_ENDPGM 0, implicit %3
+...
+
+---
+name: test_merge_values_v_s192_v_s64_v_s64_v_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+
+ ; GCN-LABEL: name: test_merge_values_v_s192_v_s64_v_s64_v_s64
+ ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+ ; GCN: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; GCN: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
+ ; GCN: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY $vgpr4_vgpr5
+ ; GCN: [[MV:%[0-9]+]]:vgpr(s192) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64)
+ ; GCN: S_ENDPGM 0, implicit [[MV]](s192)
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vgpr(s64) = COPY $vgpr4_vgpr5
+ %3:vgpr(s192) = G_MERGE_VALUES %0, %1, %2
+ S_ENDPGM 0, implicit %3
+...
+
+---
+name: test_merge_values_s_s256_s_s64_s_s64_s_s64_s_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6_sgpr7
+
+ ; GCN-LABEL: name: test_merge_values_s_s256_s_s64_s_s64_s_s64_s_s64
+ ; GCN: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6_sgpr7
+ ; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+ ; GCN: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5
+ ; GCN: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY $sgpr6_sgpr7
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_256 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3, [[COPY2]], %subreg.sub4_sub5, [[COPY3]], %subreg.sub6_sub7
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(s64) = COPY $sgpr0_sgpr1
+ %1:sgpr(s64) = COPY $sgpr2_sgpr3
+ %2:sgpr(s64) = COPY $sgpr4_sgpr5
+ %3:sgpr(s64) = COPY $sgpr6_sgpr7
+ %4:sgpr(s256) = G_MERGE_VALUES %0, %1, %2, %3
+ $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY %4
+...
+
+---
+name: test_merge_values_s_s256_s_s128_s_s128
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7
+
+ ; GCN-LABEL: name: test_merge_values_s_s256_s_s128_s_s128
+ ; GCN: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7
+ ; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_256 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1_sub2_sub3, [[COPY1]], %subreg.sub4_sub5_sub6_sub7
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ %1:sgpr(s128) = COPY $sgpr4_sgpr5_sgpr6_sgpr7
+ %2:sgpr(s256) = G_MERGE_VALUES %0, %1
+ $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY %2
+...
+
+---
+name: test_merge_values_s_s512_s_s256_s_s256
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+
+ ; GCN-LABEL: name: test_merge_values_s_s512_s_s256_s_s256
+ ; GCN: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; GCN: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_256 = COPY $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_512 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7, [[COPY1]], %subreg.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7,
+ %1:sgpr(s256) = COPY $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ %4:sgpr(s512) = G_MERGE_VALUES %0, %1
+ $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %4
+...
+
+---
+name: test_merge_values_s_s512_s_s64_s_s64_s_s64_s_s64_s_s64_s_s64_s_s64_s_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15
+
+ ; GCN-LABEL: name: test_merge_values_s_s512_s_s64_s_s64_s_s64_s_s64_s_s64_s_s64_s_s64_s_s64
+ ; GCN: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15
+ ; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+ ; GCN: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5
+ ; GCN: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY $sgpr6_sgpr7
+ ; GCN: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr8_sgpr9
+ ; GCN: [[COPY5:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11
+ ; GCN: [[COPY6:%[0-9]+]]:sreg_64_xexec = COPY $sgpr12_sgpr13
+ ; GCN: [[COPY7:%[0-9]+]]:sreg_64_xexec = COPY $sgpr14_sgpr15
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_512 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3, [[COPY2]], %subreg.sub4_sub5, [[COPY3]], %subreg.sub6_sub7, [[COPY4]], %subreg.sub8_sub9, [[COPY5]], %subreg.sub10_sub11, [[COPY6]], %subreg.sub12_sub13, [[COPY7]], %subreg.sub14_sub15
+ ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY [[REG_SEQUENCE]]
+ %0:sgpr(s64) = COPY $sgpr0_sgpr1
+ %1:sgpr(s64) = COPY $sgpr2_sgpr3
+ %2:sgpr(s64) = COPY $sgpr4_sgpr5
+ %3:sgpr(s64) = COPY $sgpr6_sgpr7
+ %4:sgpr(s64) = COPY $sgpr8_sgpr9
+ %5:sgpr(s64) = COPY $sgpr10_sgpr11
+ %6:sgpr(s64) = COPY $sgpr12_sgpr13
+ %7:sgpr(s64) = COPY $sgpr14_sgpr15
+ %8:sgpr(s512) = G_MERGE_VALUES %0, %1, %2, %3, %4, %5, %6, %7
+ $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %8
+...
+
+---
+name: test_merge_values_v_v512_v_s64_v_s64_v_s64_v_s64_v_s64_v_s64_v_s64_v_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7, $vgpr8_vgpr9, $vgpr10_vgpr11, $vgpr12_vgpr13, $vgpr14_vgpr15
+
+ ; GCN-LABEL: name: test_merge_values_v_v512_v_s64_v_s64_v_s64_v_s64_v_s64_v_s64_v_s64_v_s64
+ ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7, $vgpr8_vgpr9, $vgpr10_vgpr11, $vgpr12_vgpr13, $vgpr14_vgpr15
+ ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
+ ; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr6_vgpr7
+ ; GCN: [[COPY4:%[0-9]+]]:vreg_64 = COPY $vgpr8_vgpr9
+ ; GCN: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
+ ; GCN: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
+ ; GCN: [[COPY7:%[0-9]+]]:vreg_64 = COPY $vgpr14_vgpr15
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3, [[COPY2]], %subreg.sub4_sub5, [[COPY3]], %subreg.sub6_sub7, [[COPY4]], %subreg.sub8_sub9, [[COPY5]], %subreg.sub10_sub11, [[COPY6]], %subreg.sub12_sub13, [[COPY7]], %subreg.sub14_sub15
+ ; GCN: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[REG_SEQUENCE]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vgpr(s64) = COPY $vgpr4_vgpr5
+ %3:vgpr(s64) = COPY $vgpr6_vgpr7
+ %4:vgpr(s64) = COPY $vgpr8_vgpr9
+ %5:vgpr(s64) = COPY $vgpr10_vgpr11
+ %6:vgpr(s64) = COPY $vgpr12_vgpr13
+ %7:vgpr(s64) = COPY $vgpr14_vgpr15
+ %8:vgpr(s512) = G_MERGE_VALUES %0, %1, %2, %3, %4, %5, %6, %7
+ $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY %8
+...
+
+---
+name: test_merge_values_rc_already_set_src_v_s64_v_s32_v_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; GCN-LABEL: name: test_merge_values_rc_already_set_src_v_s64_v_s32_v_s32
+ ; GCN: liveins: $vgpr0, $vgpr1
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:vgpr_32(s32) = COPY $vgpr0
+ %1:vgpr_32(s32) = COPY $vgpr1
+ %2:vgpr(s64) = G_MERGE_VALUES %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: test_merge_values_rc_already_set_dst_v_s64_v_s32_v_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; GCN-LABEL: name: test_merge_values_rc_already_set_dst_v_s64_v_s32_v_s32
+ ; GCN: liveins: $vgpr0, $vgpr1
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vreg_64(s64) = G_MERGE_VALUES %0, %1
+ S_ENDPGM 0, implicit %2
+...
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