[llvm] r365476 - [mips] Implement sge/sgeu pseudo instructions
Simon Atanasyan via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 9 05:55:56 PDT 2019
Author: atanasyan
Date: Tue Jul 9 05:55:55 2019
New Revision: 365476
URL: http://llvm.org/viewvc/llvm-project?rev=365476&view=rev
Log:
[mips] Implement sge/sgeu pseudo instructions
The `sge/sgeu Dst, Src1, Src2/Imm` pseudo instructions set register
`Dst` to 1 if register `Src1` is greater than or equal `Src2/Imm` and
to 0 otherwise.
Differential Revision: https://reviews.llvm.org/D64314
Added:
llvm/trunk/test/MC/Mips/macro-sge.s
llvm/trunk/test/MC/Mips/macro-sge64.s
Modified:
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=365476&r1=365475&r2=365476&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Tue Jul 9 05:55:55 2019
@@ -275,6 +275,12 @@ class MipsAsmParser : public MCTargetAsm
bool expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
+ bool expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+ const MCSubtargetInfo *STI);
+
+ bool expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+ const MCSubtargetInfo *STI);
+
bool expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
@@ -2476,6 +2482,14 @@ MipsAsmParser::tryExpandInstruction(MCIn
case Mips::NORImm:
case Mips::NORImm64:
return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
+ case Mips::SGE:
+ case Mips::SGEU:
+ return expandSge(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
+ case Mips::SGEImm:
+ case Mips::SGEUImm:
+ case Mips::SGEImm64:
+ case Mips::SGEUImm64:
+ return expandSgeImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::SGTImm:
case Mips::SGTUImm:
case Mips::SGTImm64:
@@ -4292,6 +4306,96 @@ bool MipsAsmParser::expandUxw(MCInst &In
return false;
}
+
+bool MipsAsmParser::expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+ const MCSubtargetInfo *STI) {
+ MipsTargetStreamer &TOut = getTargetStreamer();
+
+ assert(Inst.getNumOperands() == 3 && "Invalid operand count");
+ assert(Inst.getOperand(0).isReg() &&
+ Inst.getOperand(1).isReg() &&
+ Inst.getOperand(2).isReg() && "Invalid instruction operand.");
+
+ unsigned DstReg = Inst.getOperand(0).getReg();
+ unsigned SrcReg = Inst.getOperand(1).getReg();
+ unsigned OpReg = Inst.getOperand(2).getReg();
+ unsigned OpCode;
+
+ warnIfNoMacro(IDLoc);
+
+ switch (Inst.getOpcode()) {
+ case Mips::SGE:
+ OpCode = Mips::SLT;
+ break;
+ case Mips::SGEU:
+ OpCode = Mips::SLTu;
+ break;
+ default:
+ llvm_unreachable("unexpected 'sge' opcode");
+ }
+
+ // $SrcReg >= $OpReg is equal to (not ($SrcReg < $OpReg))
+ TOut.emitRRR(OpCode, DstReg, SrcReg, OpReg, IDLoc, STI);
+ TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
+
+ return false;
+}
+
+bool MipsAsmParser::expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+ const MCSubtargetInfo *STI) {
+ MipsTargetStreamer &TOut = getTargetStreamer();
+
+ assert(Inst.getNumOperands() == 3 && "Invalid operand count");
+ assert(Inst.getOperand(0).isReg() &&
+ Inst.getOperand(1).isReg() &&
+ Inst.getOperand(2).isImm() && "Invalid instruction operand.");
+
+ unsigned DstReg = Inst.getOperand(0).getReg();
+ unsigned SrcReg = Inst.getOperand(1).getReg();
+ int64_t ImmValue = Inst.getOperand(2).getImm();
+ unsigned OpRegCode, OpImmCode;
+
+ warnIfNoMacro(IDLoc);
+
+ switch (Inst.getOpcode()) {
+ case Mips::SGEImm:
+ case Mips::SGEImm64:
+ OpRegCode = Mips::SLT;
+ OpImmCode = Mips::SLTi;
+ break;
+ case Mips::SGEUImm:
+ case Mips::SGEUImm64:
+ OpRegCode = Mips::SLTu;
+ OpImmCode = Mips::SLTiu;
+ break;
+ default:
+ llvm_unreachable("unexpected 'sge' opcode with immediate");
+ }
+
+ // $SrcReg >= Imm is equal to (not ($SrcReg < Imm))
+ if (isInt<16>(ImmValue)) {
+ // Use immediate version of STL.
+ TOut.emitRRI(OpImmCode, DstReg, SrcReg, ImmValue, IDLoc, STI);
+ TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
+ } else {
+ unsigned ImmReg = DstReg;
+ if (DstReg == SrcReg) {
+ unsigned ATReg = getATReg(Inst.getLoc());
+ if (!ATReg)
+ return true;
+ ImmReg = ATReg;
+ }
+
+ if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
+ false, IDLoc, Out, STI))
+ return true;
+
+ TOut.emitRRR(OpRegCode, DstReg, SrcReg, ImmReg, IDLoc, STI);
+ TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
+ }
+
+ return false;
+}
bool MipsAsmParser::expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI) {
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=365476&r1=365475&r2=365476&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Jul 9 05:55:55 2019
@@ -1155,6 +1155,20 @@ def SLTUImm64 : MipsAsmPseudoInst<(outs
def : MipsInstAlias<"sltu\t$rs, $imm", (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs,
imm64:$imm)>, GPR_64;
+def SGEImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
+ (ins GPR64Opnd:$rs, imm64:$imm),
+ "sge\t$rd, $rs, $imm">, GPR_64;
+def : MipsInstAlias<"sge $rs, $imm", (SGEImm64 GPR64Opnd:$rs,
+ GPR64Opnd:$rs,
+ imm64:$imm), 0>, GPR_64;
+
+def SGEUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
+ (ins GPR64Opnd:$rs, imm64:$imm),
+ "sgeu\t$rd, $rs, $imm">, GPR_64;
+def : MipsInstAlias<"sgeu $rs, $imm", (SGEUImm64 GPR64Opnd:$rs,
+ GPR64Opnd:$rs,
+ imm64:$imm), 0>, GPR_64;
+
def SGTImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
(ins GPR64Opnd:$rs, imm64:$imm),
"sgt\t$rd, $rs, $imm">, GPR_64;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=365476&r1=365475&r2=365476&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Jul 9 05:55:55 2019
@@ -2693,6 +2693,35 @@ let AdditionalPredicates = [NotInMicroMi
(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS1;
def : MipsInstAlias<"negu $rt",
(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>, ISA_MIPS1;
+
+ def SGE : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+ (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+ "sge\t$rd, $rs, $rt">, ISA_MIPS1;
+ def : MipsInstAlias<"sge $rs, $rt",
+ (SGE GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,
+ ISA_MIPS1;
+ def SGEImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+ (ins GPR32Opnd:$rs, simm32:$imm),
+ "sge\t$rd, $rs, $imm">, GPR_32;
+ def : MipsInstAlias<"sge $rs, $imm", (SGEImm GPR32Opnd:$rs,
+ GPR32Opnd:$rs,
+ simm32:$imm), 0>,
+ GPR_32;
+
+ def SGEU : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+ (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+ "sgeu\t$rd, $rs, $rt">, ISA_MIPS1;
+ def : MipsInstAlias<"sgeu $rs, $rt",
+ (SGEU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,
+ ISA_MIPS1;
+ def SGEUImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+ (ins GPR32Opnd:$rs, uimm32_coerced:$imm),
+ "sgeu\t$rd, $rs, $imm">, GPR_32;
+ def : MipsInstAlias<"sgeu $rs, $imm", (SGEUImm GPR32Opnd:$rs,
+ GPR32Opnd:$rs,
+ uimm32_coerced:$imm), 0>,
+ GPR_32;
+
def : MipsInstAlias<
"sgt $rd, $rs, $rt",
(SLT GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;
Added: llvm/trunk/test/MC/Mips/macro-sge.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/macro-sge.s?rev=365476&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/macro-sge.s (added)
+++ llvm/trunk/test/MC/Mips/macro-sge.s Tue Jul 9 05:55:55 2019
@@ -0,0 +1,43 @@
+# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips1 < %s | FileCheck %s
+# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips64 < %s | FileCheck %s
+
+sge $4, $5
+# CHECK: slt $4, $4, $5 # encoding: [0x00,0x85,0x20,0x2a]
+# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sge $4, $5, $6
+# CHECK: slt $4, $5, $6 # encoding: [0x00,0xa6,0x20,0x2a]
+# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sge $4, 16
+# CHECK: slti $4, $4, 16 # encoding: [0x28,0x84,0x00,0x10]
+# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sge $4, $5, 16
+# CHECK: slti $4, $5, 16 # encoding: [0x28,0xa4,0x00,0x10]
+# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sge $4, $5, 0x10000
+# CHECK: lui $4, 1 # encoding: [0x3c,0x04,0x00,0x01]
+# CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
+# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sgeu $4, $5
+# CHECK: sltu $4, $4, $5 # encoding: [0x00,0x85,0x20,0x2b]
+# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sgeu $4, $5, $6
+# CHECK: sltu $4, $5, $6 # encoding: [0x00,0xa6,0x20,0x2b]
+# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sgeu $4, 16
+# CHECK: sltiu $4, $4, 16 # encoding: [0x2c,0x84,0x00,0x10]
+# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sgeu $4, $5, 16
+# CHECK: sltiu $4, $5, 16 # encoding: [0x2c,0xa4,0x00,0x10]
+# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sgeu $4, $5, 0x10000
+# CHECK: lui $4, 1 # encoding: [0x3c,0x04,0x00,0x01]
+# CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
+# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sge $4, 0x10000
+# CHECK: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01]
+# CHECK: slt $4, $4, $1 # encoding: [0x00,0x81,0x20,0x2a]
+# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sgeu $4, 0x10000
+# CHECK: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01]
+# CHECK: sltu $4, $4, $1 # encoding: [0x00,0x81,0x20,0x2b]
+# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
Added: llvm/trunk/test/MC/Mips/macro-sge64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/macro-sge64.s?rev=365476&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/macro-sge64.s (added)
+++ llvm/trunk/test/MC/Mips/macro-sge64.s Tue Jul 9 05:55:55 2019
@@ -0,0 +1,29 @@
+# RUN: not llvm-mc -arch=mips -mcpu=mips1 < %s 2>&1 \
+# RUN: | FileCheck --check-prefix=MIPS32 %s
+# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips64 < %s \
+# RUN: | FileCheck --check-prefix=MIPS64 %s
+
+sge $4, $5, 0x100000000
+# MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+# MIPS64: ori $4, $zero, 32768 # encoding: [0x34,0x04,0x80,0x00]
+# MIPS64: dsll $4, $4, 17 # encoding: [0x00,0x04,0x24,0x78]
+# MIPS64: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
+# MIPS64: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sgeu $4, $5, 0x100000000
+# MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+# MIPS64: ori $4, $zero, 32768 # encoding: [0x34,0x04,0x80,0x00]
+# MIPS64: dsll $4, $4, 17 # encoding: [0x00,0x04,0x24,0x78]
+# MIPS64: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
+# MIPS64: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sge $4, 0x100000000
+# MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+# MIPS64: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00]
+# MIPS64: dsll $1, $1, 17 # encoding: [0x00,0x01,0x0c,0x78]
+# MIPS64: slt $4, $4, $1 # encoding: [0x00,0x81,0x20,0x2a]
+# MIPS64: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sgeu $4, 0x100000000
+# MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+# MIPS64: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00]
+# MIPS64: dsll $1, $1, 17 # encoding: [0x00,0x01,0x0c,0x78]
+# MIPS64: sltu $4, $4, $1 # encoding: [0x00,0x81,0x20,0x2b]
+# MIPS64: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
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