[PATCH] D64354: [AArch64][GlobalISel] Optimize conditional branches followed by unconditional branches

[Amara Emerson via Phabricator via llvm-commits]

aemerson created this revision.
aemerson added reviewers: paquette, arsenm, qcolombet, dsanders, aditya_nandakumar, volkan.
Herald added subscribers: Petar.Avramovic, atanasyan, jrtc27, hiraditya, kristof.beyls, javed.absar, rovka, nhaehnle, wdng, jvesely, sdardis.
Herald added a project: LLVM.

If we have an icmp->brcond->br sequence where the brcond just branches to the
next block jumping over the br, while the br takes the false edge, then we can
emit a Bcc conditional branch to the br's target while inverting the condition.
This means we can eliminate the br as an unconditional branch and also avoid
generating a cset.

This also makes the InstructionSelector instances non-const, because we need to
be able to communicate to the InstructionSelect pass that certain generic
instructions should be deleted. We can't delete these from inside the target
specific selector classes because it would invalidate iterators held up the
call stack. Therefore, the select() virtual functions are no longer const,
but I think this is reasonable.

Improves code size on arm64 -O0 on CTMark by 4.3%.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D64354

Files:
  llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
  llvm/include/llvm/CodeGen/MachineOperand.h
  llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
  llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
  llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
  llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
  llvm/lib/Target/ARM/ARMInstructionSelector.cpp
  llvm/lib/Target/ARM/ARMSubtarget.cpp
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/Mips/MipsInstructionSelector.cpp
  llvm/lib/Target/Mips/MipsSubtarget.cpp
  llvm/lib/Target/Mips/MipsSubtarget.h
  llvm/lib/Target/X86/X86InstructionSelector.cpp
  llvm/lib/Target/X86/X86Subtarget.cpp
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/AArch64/GlobalISel/opt-br-brcond.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir

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