[PATCH] D61259: AArch64: support arm64_32, an ILP32 slice for watchOS.

Mon Jul 8 05:29:41 PDT 2019

t.p.northover marked an inline comment as done.
t.p.northover added inline comments.

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Comment at: llvm/test/CodeGen/AArch64/win64_vararg.ll:271
+; CHECK: mov     x1, [[REG2]]
+; CHECK: mov     x3, [[REG3]]
 ; CHECK: str     x30, [sp, #16]
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t.p.northover wrote:
> efriedma wrote:
> > There isn't any obvious reason for this test to change?
> I think it's because of the `std::map` change you called out above. It implicitly sorts the list of registers that get copied, perturbing the DAG and scheduling.
> 
> I think I'll switch it back to `SmallVector` and use `std::find_if` to handle the (rare) ARM compatibility instead. It ought to be faster in the common case and won't have this side-effect.
Well, as you can see that accounted for a lot of the differences, but the `fmov`s still get reordered w.r.t. the store. I have no idea why this is: the DAG is identical and I'm reasonably sure it's harmless so I blame gremlins.

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  https://reviews.llvm.org/D61259/new/

https://reviews.llvm.org/D61259