[PATCH] D64295: [X86][AMDGPU] Add an out parameter to isLoadBitCastBeneficial/isStoreBitCastBeneficial to indicate we shouldn't both checking the alignment.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel, arsenm.
Herald added subscribers: hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.

Basically the problem is that X86 doesn't set the Fast flag from
allowsMemoryAccess on certain CPUs due to slow unaligned memory
subtarget features. This prevents bitcasts from being folded into
loads and stores. But all vector loads and stores of the same width
are the same cost on X86.

By adding this flag to the bitcast routines we can prevent the
allowsMemoryAccess from being called and just let the fold
happen. This may not be the best solution but it didn't require
very many changes since allowsMemoryAccess is used in other places
where alignment is important.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D64295

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/test/CodeGen/X86/merge-consecutive-stores-nt.ll
  llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll

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