[PATCH] D64167: [TargetLowering] support BlockAddress as "i" inline asm constraint

[Nick Desaulniers via Phabricator via llvm-commits]

nickdesaulniers updated this revision to Diff 207914.
nickdesaulniers added a comment.

- git-clang-format HEAD~


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D64167/new/

https://reviews.llvm.org/D64167

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/inline-asm-i-constraint-i1.ll


Index: llvm/test/CodeGen/AArch64/inline-asm-i-constraint-i1.ll
===================================================================
--- llvm/test/CodeGen/AArch64/inline-asm-i-constraint-i1.ll
+++ llvm/test/CodeGen/AArch64/inline-asm-i-constraint-i1.ll
@@ -1,14 +1,25 @@
 ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
 
 ; Make sure that boolean immediates are properly (zero) extended.
+; CHECK-LABEL: foo:
 ; CHECK: TEST 42 + 1 - .
 
 target triple = "aarch64-unknown-linux-gnu"
 
-define i32 @foo() #0 {
+define i32 @foo() {
 entry:
   tail call void asm sideeffect "#TEST 42 + ${0:c} - .\0A\09", "i,~{dirflag},~{fpsr},~{flags}"(i1 true) #0
   ret i32 1
 }
 
-attributes #0 = { nounwind }
+; CHECK-LABEL: bar:
+; CHECK: TEST .Ltmp0
+define void @bar() {
+entry:
+  br label %baz
+baz:
+  call void asm sideeffect "#TEST $0", "i,~{dirflag},~{fpsr},~{flags}"(i8* blockaddress(@bar, %baz))
+  ret void
+indirectgoto:
+  indirectbr i8* undef, [label %baz]
+}
Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -3652,6 +3652,7 @@
 
     GlobalAddressSDNode *GA;
     ConstantSDNode *C;
+    BlockAddressSDNode *BA;
     uint64_t Offset = 0;
 
     // Match (GA) or (C) or (GA+C) or (GA-C) or ((GA+C)+C) or (((GA+C)+C)+C),
@@ -3679,6 +3680,12 @@
         Ops.push_back(DAG.getTargetConstant(Offset + ExtVal,
                                             SDLoc(C), MVT::i64));
         return;
+      } else if ((BA = dyn_cast<BlockAddressSDNode>(Op)) &&
+                 ConstraintLetter != 'n') {
+        Ops.push_back(DAG.getTargetBlockAddress(
+            BA->getBlockAddress(), BA->getValueType(0),
+            Offset + BA->getOffset(), BA->getTargetFlags()));
+        return;
       } else {
         const unsigned OpCode = Op.getOpcode();
         if (OpCode == ISD::ADD || OpCode == ISD::SUB) {


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