[llvm] r365093 - GlobalISel: Fix widenScalar for pointer typed G_MERGE_VALUES

Wed Jul 3 16:08:07 PDT 2019

Author: arsenm
Date: Wed Jul  3 16:08:06 2019
New Revision: 365093

URL: http://llvm.org/viewvc/llvm-project?rev=365093&view=rev
Log:
GlobalISel: Fix widenScalar for pointer typed G_MERGE_VALUES

Modified:
    llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir

Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp?rev=365093&r1=365092&r2=365093&view=diff
==============================================================================

--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Wed Jul  3 16:08:06 2019
@@ -791,7 +791,7 @@ LegalizerHelper::widenScalarMergeValues(
 
   Register DstReg = MI.getOperand(0).getReg();
   LLT DstTy = MRI.getType(DstReg);
-  if (!DstTy.isScalar())
+  if (DstTy.isVector())
     return UnableToLegalize;
 
   Register Src1 = MI.getOperand(1).getReg();

Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir?rev=365093&r1=365092&r2=365093&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir Wed Jul  3 16:08:06 2019
@@ -2,6 +2,89 @@
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
+name: test_merge_p1_s8
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7
+    ; CHECK-LABEL: name: test_merge_p1_s8
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
+    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
+    ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+    ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C2]]
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[AND]](s32)
+    ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C2]]
+    ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
+    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[COPY11]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR]](s32)
+    ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+    ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
+    ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C2]]
+    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[AND3]](s32)
+    ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
+    ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C2]]
+    ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
+    ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[COPY15]]
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
+    ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+    ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C1]]
+    ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
+    ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C2]]
+    ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[AND6]](s32)
+    ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
+    ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C2]]
+    ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[SHL2]](s32)
+    ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[COPY19]]
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[OR2]](s32)
+    ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+    ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C1]]
+    ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
+    ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C2]]
+    ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[AND9]](s32)
+    ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
+    ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C2]]
+    ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[SHL3]](s32)
+    ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND11]], [[COPY23]]
+    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[OR3]](s32)
+    ; CHECK: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](p1)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = COPY $vgpr1
+    %2:_(s32) = COPY $vgpr2
+    %3:_(s32) = COPY $vgpr3
+    %4:_(s32) = COPY $vgpr4
+    %5:_(s32) = COPY $vgpr5
+    %6:_(s32) = COPY $vgpr6
+    %7:_(s32) = COPY $vgpr7
+    %8:_(s8) = G_TRUNC %0
+    %9:_(s8) = G_TRUNC %1
+    %10:_(s8) = G_TRUNC %2
+    %11:_(s8) = G_TRUNC %3
+    %12:_(s8) = G_TRUNC %4
+    %13:_(s8) = G_TRUNC %5
+    %14:_(s8) = G_TRUNC %6
+    %15:_(s8) = G_TRUNC %7
+    %16:_(p1) = G_MERGE_VALUES %8, %9, %10, %11, %12, %13, %14, %15
+    $vgpr0_vgpr1 = COPY %16
+
+...
+
+---
 name: test_merge_s16_s8_s8
 body: |
   bb.0:


