[PATCH] D52165: [RISCV] Support RISC-V in getBitcodeMachineKind

[Phabricator via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL364996: [ELF][RISCV] Support RISC-V in getBitcodeMachineKind (authored by kito, committed by ).
Herald added a subscriber: jrtc27.

Changed prior to commit:
  https://reviews.llvm.org/D52165?vs=207474&id=207699#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D52165/new/

https://reviews.llvm.org/D52165

Files:
  lld/trunk/ELF/InputFiles.cpp
  lld/trunk/test/ELF/lto/riscv32.ll
  lld/trunk/test/ELF/lto/riscv64.ll


Index: lld/trunk/ELF/InputFiles.cpp
===================================================================
--- lld/trunk/ELF/InputFiles.cpp
+++ lld/trunk/ELF/InputFiles.cpp
@@ -1402,6 +1402,9 @@
   case Triple::ppc64:
   case Triple::ppc64le:
     return EM_PPC64;
+  case Triple::riscv32:
+  case Triple::riscv64:
+    return EM_RISCV;
   case Triple::x86:
     return T.isOSIAMCU() ? EM_IAMCU : EM_386;
   case Triple::x86_64:
Index: lld/trunk/test/ELF/lto/riscv32.ll
===================================================================
--- lld/trunk/test/ELF/lto/riscv32.ll
+++ lld/trunk/test/ELF/lto/riscv32.ll
@@ -0,0 +1,10 @@
+; REQUIRES: riscv
+
+; RUN: llvm-as %s -o %t.o
+; RUN: ld.lld %t.o -o %t
+target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
+target triple = "riscv32-unknown-elf"
+
+define void @f() {
+  ret void
+}
Index: lld/trunk/test/ELF/lto/riscv64.ll
===================================================================
--- lld/trunk/test/ELF/lto/riscv64.ll
+++ lld/trunk/test/ELF/lto/riscv64.ll
@@ -0,0 +1,10 @@
+; REQUIRES: riscv
+
+; RUN: llvm-as %s -o %t.o
+; RUN: ld.lld %t.o -o %t
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
+target triple = "riscv64-unknown-elf"
+
+define void @f() {
+  ret void
+}


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