[PATCH] D61289: [globalisel] Add G_SEXT_INREG

[Daniel Sanders via Phabricator via llvm-commits]

dsanders updated this revision to Diff 207863.
dsanders marked 3 inline comments as done.
dsanders added a comment.

- EXPECT_EQ argument order


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61289/new/

https://reviews.llvm.org/D61289

Files:
  llvm/include/llvm/CodeGen/GlobalISel/ConstantFoldingMIRBuilder.h
  llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
  llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
  llvm/include/llvm/CodeGen/GlobalISel/Utils.h
  llvm/include/llvm/MC/MCInstrDesc.h
  llvm/include/llvm/Support/TargetOpcodes.def
  llvm/include/llvm/Target/GenericOpcodes.td
  llvm/include/llvm/Target/Target.td
  llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
  llvm/lib/CodeGen/GlobalISel/Utils.cpp
  llvm/lib/CodeGen/MachineVerifier.cpp
  llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
  llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
  llvm/lib/Target/X86/X86LegalizerInfo.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extends.ll
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir
  llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
  llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-exts.mir
  llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
  llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir
  llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
  llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir
  llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
  llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
  llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir
  llvm/test/MachineVerifier/test_g_sext_inreg.mir
  llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
  llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp

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