[llvm] r365063 - [GlobalISel][AArch64] Use getConstantVRegValWithLookThrough for selectArithImmed
Jessica Paquette via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 3 10:46:24 PDT 2019
Author: paquette
Date: Wed Jul 3 10:46:23 2019
New Revision: 365063
URL: http://llvm.org/viewvc/llvm-project?rev=365063&view=rev
Log:
[GlobalISel][AArch64] Use getConstantVRegValWithLookThrough for selectArithImmed
Instead of just stopping to see if we have a G_CONSTANT, instead, look through
G_TRUNCs, G_SEXTs, and G_ZEXTs.
This gives an average ~1.3% code size improvement on CINT2000 at -O3.
Differential Revision: https://reviews.llvm.org/D64108
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-cmp.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=365063&r1=365062&r2=365063&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Wed Jul 3 10:46:23 2019
@@ -3777,13 +3777,11 @@ static Optional<uint64_t> getImmedFromMO
else if (Root.isCImm())
Immed = Root.getCImm()->getZExtValue();
else if (Root.isReg()) {
- MachineInstr *Def = MRI.getVRegDef(Root.getReg());
- if (Def->getOpcode() != TargetOpcode::G_CONSTANT)
+ auto ValAndVReg =
+ getConstantVRegValWithLookThrough(Root.getReg(), MRI, true);
+ if (!ValAndVReg)
return None;
- MachineOperand &Op1 = Def->getOperand(1);
- if (!Op1.isCImm() || Op1.getCImm()->getBitWidth() > 64)
- return None;
- Immed = Op1.getCImm()->getZExtValue();
+ Immed = ValAndVReg->Value;
} else
return None;
return Immed;
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-cmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-cmp.mir?rev=365063&r1=365062&r2=365063&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-cmp.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-cmp.mir Wed Jul 3 10:46:23 2019
@@ -70,3 +70,47 @@ body: |
RET_ReallyLR implicit $w0
...
+---
+name: cmp_imm_lookthrough
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $w0
+ ; CHECK-LABEL: name: cmp_imm_lookthrough
+ ; CHECK: liveins: $w0
+ ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
+ ; CHECK: $wzr = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv
+ ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
+ ; CHECK: $w0 = COPY [[CSINCWr]]
+ ; CHECK: RET_ReallyLR implicit $w0
+ %0:gpr(s32) = COPY $w0
+ %1:gpr(s64) = G_CONSTANT i64 42
+ %2:gpr(s32) = G_TRUNC %1(s64)
+ %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
+ $w0 = COPY %5(s32)
+ RET_ReallyLR implicit $w0
+
+...
+---
+name: cmp_imm_lookthrough_bad_trunc
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $w0
+ ; CHECK-LABEL: name: cmp_imm_lookthrough_bad_trunc
+ ; CHECK: liveins: $w0
+ ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
+ ; CHECK: $wzr = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
+ ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
+ ; CHECK: $w0 = COPY [[CSINCWr]]
+ ; CHECK: RET_ReallyLR implicit $w0
+ %0:gpr(s32) = COPY $w0
+ %1:gpr(s64) = G_CONSTANT i64 68719476736 ; 0x1000000000
+ %2:gpr(s32) = G_TRUNC %1(s64) ; Value truncates to 0
+ %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
+ $w0 = COPY %5(s32)
+ RET_ReallyLR implicit $w0
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir?rev=365063&r1=365062&r2=365063&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir Wed Jul 3 10:46:23 2019
@@ -57,19 +57,16 @@ body: |
; CHECK: successors: %bb.4(0x40000000), %bb.1(0x40000000)
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
- ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 71
- ; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 0
+ ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 4, 0, implicit-def $nzcv
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[SUBSWri]], %subreg.sub_32
- ; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
- ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
- ; CHECK: [[UBFMXri1:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG1]], 0, 31
- ; CHECK: $xzr = SUBSXrr [[UBFMXri]], [[UBFMXri1]], implicit-def $nzcv
+ ; CHECK: [[UBFMXri:%[0-9]+]]:gpr64common = UBFMXri [[SUBREG_TO_REG]], 0, 31
+ ; CHECK: $xzr = SUBSXri [[UBFMXri]], 71, 0, implicit-def $nzcv
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
; CHECK: TBNZW [[CSINCWr]], 0, %bb.4
; CHECK: bb.1.entry:
; CHECK: successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab)
- ; CHECK: [[MOVi32imm2:%[0-9]+]]:gpr32 = MOVi32imm 0
+ ; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVaddrJT:%[0-9]+]]:gpr64 = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
; CHECK: early-clobber %18:gpr64, early-clobber %19:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[UBFMXri]], %jump-table.0
; CHECK: BR %18
@@ -79,10 +76,10 @@ body: |
; CHECK: B %bb.4
; CHECK: bb.3.sw.bb1:
; CHECK: successors: %bb.4(0x80000000)
- ; CHECK: [[MOVi32imm3:%[0-9]+]]:gpr32 = MOVi32imm 3
- ; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[MOVi32imm3]], $wzr
+ ; CHECK: [[MOVi32imm2:%[0-9]+]]:gpr32 = MOVi32imm 3
+ ; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[MOVi32imm2]], $wzr
; CHECK: bb.4.return:
- ; CHECK: [[PHI:%[0-9]+]]:gpr32 = PHI [[MADDWrrr]], %bb.3, [[ADDWri]], %bb.2, [[MOVi32imm1]], %bb.0, [[MOVi32imm2]], %bb.1
+ ; CHECK: [[PHI:%[0-9]+]]:gpr32 = PHI [[MADDWrrr]], %bb.3, [[ADDWri]], %bb.2, [[MOVi32imm]], %bb.0, [[MOVi32imm1]], %bb.1
; CHECK: $w0 = COPY [[PHI]]
; CHECK: RET_ReallyLR implicit $w0
bb.1.entry:
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