[PATCH] D61289: [globalisel] Add G_SEXT_INREG

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D61289#1568751 <https://reviews.llvm.org/D61289#1568751>, @dsanders wrote:

>


. Do any targets allow both the position and width to be specified as registers?

Both the offset and width can be registers on AMDGPU (for the SALU version they are both packed in one register)


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