[PATCH] D63411: [RISCV] Specify registers used in DWARF exception handling

[Alex Bradbury via Phabricator via llvm-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

I think you might as well add RV32 and RV64 CHECK prefixes and put the test through update_llc_test_checks.py to ensure the generated code is sane, but with that change this is good to land. Thanks!


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https://reviews.llvm.org/D63411