[PATCH] D64124: [PowerPC] Hardware Loop branch instruction's condition may not be icmp

[ChenZheng via Phabricator via llvm-commits]

shchenz updated this revision to Diff 207770.
shchenz added a comment.

@samparker Thanks for your comment, Sam. Updated the patch. I use the same source in both opt test and llc test, since the testing point is not the same, hope this is ok.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D64124/new/

https://reviews.llvm.org/D64124

Files:
  llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
  llvm/test/CodeGen/PowerPC/pr42492.ll
  llvm/test/Transforms/HardwareLoops/unscevable.ll


Index: llvm/test/Transforms/HardwareLoops/unscevable.ll
===================================================================
--- llvm/test/Transforms/HardwareLoops/unscevable.ll
+++ llvm/test/Transforms/HardwareLoops/unscevable.ll
@@ -45,3 +45,35 @@
 while.end:
   ret void
 }
+
+; CHECK-LABEL: variant_counter2
+; CHECK-NOT: set.loop.iterations
+; CHECK-NOT: loop.decrement
+define void @variant_counter2(i8*, i8*, i64*) {
+  %4 = icmp eq i8* %0, %1
+  br i1 %4, label %9, label %5
+
+5:                                                ; preds = %3
+  %6 = getelementptr inbounds i64, i64* %2, i64 1
+  %7 = load i64, i64* %6, align 8
+  br label %10
+
+8:                                                ; preds = %10
+  store i64 %14, i64* %6, align 8
+  br label %9
+
+9:                                                ; preds = %8, %3
+  ret void
+
+10:                                               ; preds = %5, %10
+  %11 = phi i64 [ %7, %5 ], [ %14, %10 ]
+  %12 = phi i32 [ 0, %5 ], [ %15, %10 ]
+  %13 = phi i8* [ %0, %5 ], [ %16, %10 ]
+  %14 = shl nsw i64 %11, 4
+  %15 = add nuw nsw i32 %12, 1
+  %16 = getelementptr inbounds i8, i8* %13, i64 1
+  %17 = icmp ugt i32 %12, 14
+  %18 = icmp eq i8* %16, %1
+  %19 = or i1 %18, %17
+  br i1 %19, label %8, label %10
+}
Index: llvm/test/CodeGen/PowerPC/pr42492.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/pr42492.ll
@@ -0,0 +1,33 @@
+; REQUIRES: asserts
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
+
+; Check we don't assert.
+; CHECK-LABEL: f:
+define void @f(i8*, i8*, i64*) {
+  %4 = icmp eq i8* %0, %1
+  br i1 %4, label %9, label %5
+
+5:                                                ; preds = %3
+  %6 = getelementptr inbounds i64, i64* %2, i64 1
+  %7 = load i64, i64* %6, align 8
+  br label %10
+
+8:                                                ; preds = %10
+  store i64 %14, i64* %6, align 8
+  br label %9
+
+9:                                                ; preds = %8, %3
+  ret void
+
+10:                                               ; preds = %5, %10
+  %11 = phi i64 [ %7, %5 ], [ %14, %10 ]
+  %12 = phi i32 [ 0, %5 ], [ %15, %10 ]
+  %13 = phi i8* [ %0, %5 ], [ %16, %10 ]
+  %14 = shl nsw i64 %11, 4
+  %15 = add nuw nsw i32 %12, 1
+  %16 = getelementptr inbounds i8, i8* %13, i64 1
+  %17 = icmp ugt i32 %12, 14
+  %18 = icmp eq i8* %16, %1
+  %19 = or i1 %18, %17
+  br i1 %19, label %8, label %10
+}
Index: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
===================================================================
--- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+++ llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
@@ -3269,7 +3269,7 @@
       if (CI->isEquality()) {
         // If CI can be saved in some target, like replaced inside hardware loop
         // in PowerPC, no need to generate initial formulae for it.
-        if (SaveCmp && CI == cast<ICmpInst>(ExitBranch->getCondition()))
+        if (SaveCmp && CI == dyn_cast<ICmpInst>(ExitBranch->getCondition()))
           continue;
         // Swap the operands if needed to put the OperandValToReplace on the
         // left, for consistency.


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