[PATCH] D30324: [ARM] Thumb2: favor R4-R7 over R12/LR in allocation order when opt for minsize

[Oliver Stannard (Linaro) via Phabricator via llvm-commits]

ostannard updated this revision to Diff 207731.
ostannard added a comment.

- Add a PhysReg parameter to ignoreCSRForAllocationOrder
- Check that the register is a GPR in the ARM implementation. The other register classes have the callee-saved regs last, so this doesn't make any difference to the generated code, but might avoid surprising behaviour in the future.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D30324/new/

https://reviews.llvm.org/D30324

Files:
  llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
  llvm/lib/CodeGen/RegisterClassInfo.cpp
  llvm/lib/Target/ARM/ARMRegisterInfo.td
  llvm/lib/Target/ARM/ARMSubtarget.cpp
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll
  llvm/test/CodeGen/ARM/favor-low-reg-for-Osize.ll

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