[PATCH] D61259: AArch64: support arm64_32, an ILP32 slice for watchOS.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:9747
+    if (Res.getOpcode() == ISD::AssertZext)
+      Res = Res.getOperand(0);
+
----------------
Does this have any practical effect for other targets?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:3736
 
-  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
+  std::map<unsigned, SDValue> RegsToPass;
   SmallVector<SDValue, 8> MemOpChains;
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What's changing here?  Does it make sense to add any comments?


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Comment at: llvm/test/CodeGen/AArch64/tail-call.ll:4
 declare fastcc void @callee_stack0()
-declare fastcc void @callee_stack8([8 x i32], i64)
-declare fastcc void @callee_stack16([8 x i32], i64, i64)
+declare fastcc void @callee_stack8([8 x i64], i64)
+declare fastcc void @callee_stack16([8 x i64], i64, i64)
----------------
What are you trying to do here?


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Comment at: llvm/test/CodeGen/AArch64/win64_vararg.ll:271
+; CHECK: mov     x1, [[REG2]]
+; CHECK: mov     x3, [[REG3]]
 ; CHECK: str     x30, [sp, #16]
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There isn't any obvious reason for this test to change?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61259/new/

https://reviews.llvm.org/D61259