[llvm] r364926 - GlobalISel: Add G_FENCE
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 2 07:16:40 PDT 2019
Author: arsenm
Date: Tue Jul 2 07:16:39 2019
New Revision: 364926
URL: http://llvm.org/viewvc/llvm-project?rev=364926&view=rev
Log:
GlobalISel: Add G_FENCE
The pattern importer is for some reason emitting checks for G_CONSTANT
for the immediate operands.
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
Modified:
llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h
llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
llvm/trunk/include/llvm/Support/TargetOpcodes.def
llvm/trunk/include/llvm/Target/GenericOpcodes.td
llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h?rev=364926&r1=364925&r2=364926&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h Tue Jul 2 07:16:39 2019
@@ -448,6 +448,7 @@ private:
bool translateAtomicCmpXchg(const User &U, MachineIRBuilder &MIRBuilder);
bool translateAtomicRMW(const User &U, MachineIRBuilder &MIRBuilder);
+ bool translateFence(const User &U, MachineIRBuilder &MIRBuilder);
// Stubs to keep the compiler happy while we implement the rest of the
// translation.
@@ -463,9 +464,6 @@ private:
bool translateCatchSwitch(const User &U, MachineIRBuilder &MIRBuilder) {
return false;
}
- bool translateFence(const User &U, MachineIRBuilder &MIRBuilder) {
- return false;
- }
bool translateAddrSpaceCast(const User &U, MachineIRBuilder &MIRBuilder) {
return translateCast(TargetOpcode::G_ADDRSPACE_CAST, U, MIRBuilder);
}
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h?rev=364926&r1=364925&r2=364926&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h Tue Jul 2 07:16:39 2019
@@ -1136,6 +1136,9 @@ public:
MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr,
Register Val, MachineMemOperand &MMO);
+ /// Build and insert `G_FENCE Ordering, Scope`.
+ MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope);
+
/// Build and insert \p Res = G_BLOCK_ADDR \p BA
///
/// G_BLOCK_ADDR computes the address of a basic block.
Modified: llvm/trunk/include/llvm/Support/TargetOpcodes.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetOpcodes.def?rev=364926&r1=364925&r2=364926&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/TargetOpcodes.def (original)
+++ llvm/trunk/include/llvm/Support/TargetOpcodes.def Tue Jul 2 07:16:39 2019
@@ -316,6 +316,9 @@ HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN)
HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX)
HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN)
+// Generic atomic fence
+HANDLE_TARGET_OPCODE(G_FENCE)
+
/// Generic conditional branch instruction.
HANDLE_TARGET_OPCODE(G_BRCOND)
Modified: llvm/trunk/include/llvm/Target/GenericOpcodes.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GenericOpcodes.td?rev=364926&r1=364925&r2=364926&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/GenericOpcodes.td (original)
+++ llvm/trunk/include/llvm/Target/GenericOpcodes.td Tue Jul 2 07:16:39 2019
@@ -743,6 +743,12 @@ def G_ATOMICRMW_MIN : G_ATOMICRMW_OP;
def G_ATOMICRMW_UMAX : G_ATOMICRMW_OP;
def G_ATOMICRMW_UMIN : G_ATOMICRMW_OP;
+def G_FENCE : GenericInstruction {
+ let OutOperandList = (outs);
+ let InOperandList = (ins i32imm:$ordering, i32imm:$scope);
+ let hasSideEffects = 1;
+}
+
//------------------------------------------------------------------------------
// Variadic ops
//------------------------------------------------------------------------------
Modified: llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td?rev=364926&r1=364925&r2=364926&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td (original)
+++ llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td Tue Jul 2 07:16:39 2019
@@ -136,6 +136,7 @@ def : GINodeEquiv<G_ATOMICRMW_MIN, atomi
def : GINodeEquiv<G_ATOMICRMW_MAX, atomic_load_max>;
def : GINodeEquiv<G_ATOMICRMW_UMIN, atomic_load_umin>;
def : GINodeEquiv<G_ATOMICRMW_UMAX, atomic_load_umax>;
+def : GINodeEquiv<G_FENCE, atomic_fence>;
// Specifies the GlobalISel equivalents for SelectionDAG's ComplexPattern.
// Should be used on defs that subclass GIComplexOperandMatcher<>.
Modified: llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp?rev=364926&r1=364925&r2=364926&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp Tue Jul 2 07:16:39 2019
@@ -2029,6 +2029,14 @@ bool IRTranslator::translateAtomicRMW(co
return true;
}
+bool IRTranslator::translateFence(const User &U,
+ MachineIRBuilder &MIRBuilder) {
+ const FenceInst &Fence = cast<FenceInst>(U);
+ MIRBuilder.buildFence(static_cast<unsigned>(Fence.getOrdering()),
+ Fence.getSyncScopeID());
+ return true;
+}
+
void IRTranslator::finishPendingPhis() {
#ifndef NDEBUG
DILocationVerifier Verifier;
Modified: llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp?rev=364926&r1=364925&r2=364926&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp Tue Jul 2 07:16:39 2019
@@ -851,6 +851,13 @@ MachineIRBuilder::buildAtomicRMWUmin(Reg
}
MachineInstrBuilder
+MachineIRBuilder::buildFence(unsigned Ordering, unsigned Scope) {
+ return buildInstr(TargetOpcode::G_FENCE)
+ .addImm(Ordering)
+ .addImm(Scope);
+}
+
+MachineInstrBuilder
MachineIRBuilder::buildBlockAddress(Register Res, const BlockAddress *BA) {
#ifndef NDEBUG
assert(getMRI()->getType(Res).isPointer() && "invalid res type");
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir?rev=364926&r1=364925&r2=364926&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir Tue Jul 2 07:16:39 2019
@@ -144,6 +144,9 @@
# DEBUG-NEXT: G_ATOMICRMW_UMIN (opcode {{[0-9]+}}): 2 type indices
# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
#
+# DEBUG-NEXT: G_FENCE (opcode {{[0-9]+}}): 0 type indices
+# DEBUG: .. type index coverage check SKIPPED: no rules defined
+#
# DEBUG-NEXT: G_BRCOND (opcode {{[0-9]+}}): 1 type index
# DEBUG: .. the first uncovered type index: 1, OK
#
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll?rev=364926&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll Tue Jul 2 07:16:39 2019
@@ -0,0 +1,361 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s
+
+define amdgpu_kernel void @system_one_as_acquire() {
+ ; CHECK-LABEL: name: system_one_as_acquire
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 4, 2
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("one-as") acquire
+ ret void
+}
+
+define amdgpu_kernel void @system_one_as_release() {
+ ; CHECK-LABEL: name: system_one_as_release
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 5, 2
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("one-as") release
+ ret void
+}
+
+define amdgpu_kernel void @system_one_as_acq_rel() {
+ ; CHECK-LABEL: name: system_one_as_acq_rel
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 6, 2
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("one-as") acq_rel
+ ret void
+}
+
+define amdgpu_kernel void @system_one_as_seq_cst() {
+ ; CHECK-LABEL: name: system_one_as_seq_cst
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 7, 2
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("one-as") seq_cst
+ ret void
+}
+
+define amdgpu_kernel void @singlethread_one_as_acquire() {
+ ; CHECK-LABEL: name: singlethread_one_as_acquire
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 4, 3
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("singlethread-one-as") acquire
+ ret void
+}
+
+define amdgpu_kernel void @singlethread_one_as_release() {
+ ; CHECK-LABEL: name: singlethread_one_as_release
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 5, 3
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("singlethread-one-as") release
+ ret void
+}
+
+define amdgpu_kernel void @singlethread_one_as_acq_rel() {
+ ; CHECK-LABEL: name: singlethread_one_as_acq_rel
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 6, 3
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("singlethread-one-as") acq_rel
+ ret void
+}
+
+define amdgpu_kernel void @singlethread_one_as_seq_cst() {
+ ; CHECK-LABEL: name: singlethread_one_as_seq_cst
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 7, 3
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("singlethread-one-as") seq_cst
+ ret void
+}
+
+define amdgpu_kernel void @agent_one_as_acquire() {
+ ; CHECK-LABEL: name: agent_one_as_acquire
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 4, 4
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("agent-one-as") acquire
+ ret void
+}
+
+define amdgpu_kernel void @agent_one_as_release() {
+ ; CHECK-LABEL: name: agent_one_as_release
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 5, 4
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("agent-one-as") release
+ ret void
+}
+
+define amdgpu_kernel void @agent_one_as_acq_rel() {
+ ; CHECK-LABEL: name: agent_one_as_acq_rel
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 6, 4
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("agent-one-as") acq_rel
+ ret void
+}
+
+define amdgpu_kernel void @agent_one_as_seq_cst() {
+ ; CHECK-LABEL: name: agent_one_as_seq_cst
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 7, 4
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("agent-one-as") seq_cst
+ ret void
+}
+
+define amdgpu_kernel void @workgroup_one_as_acquire() {
+ ; CHECK-LABEL: name: workgroup_one_as_acquire
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 4, 5
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("workgroup-one-as") acquire
+ ret void
+}
+
+define amdgpu_kernel void @workgroup_one_as_release() {
+ ; CHECK-LABEL: name: workgroup_one_as_release
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 5, 5
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("workgroup-one-as") release
+ ret void
+}
+
+define amdgpu_kernel void @workgroup_one_as_acq_rel() {
+ ; CHECK-LABEL: name: workgroup_one_as_acq_rel
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 6, 5
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("workgroup-one-as") acq_rel
+ ret void
+}
+
+define amdgpu_kernel void @workgroup_one_as_seq_cst() {
+ ; CHECK-LABEL: name: workgroup_one_as_seq_cst
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 7, 5
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("workgroup-one-as") seq_cst
+ ret void
+}
+
+define amdgpu_kernel void @wavefront_one_as_acquire() {
+ ; CHECK-LABEL: name: wavefront_one_as_acquire
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 4, 6
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("wavefront-one-as") acquire
+ ret void
+}
+
+define amdgpu_kernel void @wavefront_one_as_release() {
+ ; CHECK-LABEL: name: wavefront_one_as_release
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 5, 6
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("wavefront-one-as") release
+ ret void
+}
+
+define amdgpu_kernel void @wavefront_one_as_acq_rel() {
+ ; CHECK-LABEL: name: wavefront_one_as_acq_rel
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 6, 6
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("wavefront-one-as") acq_rel
+ ret void
+}
+
+define amdgpu_kernel void @wavefront_one_as_seq_cst() {
+ ; CHECK-LABEL: name: wavefront_one_as_seq_cst
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 7, 6
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("wavefront-one-as") seq_cst
+ ret void
+}
+
+define amdgpu_kernel void @system_acquire() {
+ ; CHECK-LABEL: name: system_acquire
+ ; CHECK: bb.1.entry:
+ ; CHECK: S_ENDPGM 0
+entry:
+ ret void
+}
+
+define amdgpu_kernel void @system_release() {
+ ; CHECK-LABEL: name: system_release
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 5, 1
+ ; CHECK: S_ENDPGM 0
+ fence release
+ ret void
+}
+
+define amdgpu_kernel void @system_acq_rel() {
+ ; CHECK-LABEL: name: system_acq_rel
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 6, 1
+ ; CHECK: S_ENDPGM 0
+ fence acq_rel
+ ret void
+}
+
+define amdgpu_kernel void @system_seq_cst() {
+ ; CHECK-LABEL: name: system_seq_cst
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 7, 1
+ ; CHECK: S_ENDPGM 0
+ fence seq_cst
+ ret void
+}
+
+define amdgpu_kernel void @singlethread_acquire() {
+ ; CHECK-LABEL: name: singlethread_acquire
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 4, 0
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("singlethread") acquire
+ ret void
+}
+
+define amdgpu_kernel void @singlethread_release() {
+ ; CHECK-LABEL: name: singlethread_release
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 5, 0
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("singlethread") release
+ ret void
+}
+
+define amdgpu_kernel void @singlethread_acq_rel() {
+ ; CHECK-LABEL: name: singlethread_acq_rel
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 6, 0
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("singlethread") acq_rel
+ ret void
+}
+
+define amdgpu_kernel void @singlethread_seq_cst() {
+ ; CHECK-LABEL: name: singlethread_seq_cst
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 7, 0
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("singlethread") seq_cst
+ ret void
+}
+
+define amdgpu_kernel void @agent_acquire() {
+ ; CHECK-LABEL: name: agent_acquire
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 4, 7
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("agent") acquire
+ ret void
+}
+
+define amdgpu_kernel void @agent_release() {
+ ; CHECK-LABEL: name: agent_release
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 5, 7
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("agent") release
+ ret void
+}
+
+define amdgpu_kernel void @agent_acq_rel() {
+ ; CHECK-LABEL: name: agent_acq_rel
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 6, 7
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("agent") acq_rel
+ ret void
+}
+
+define amdgpu_kernel void @agent_seq_cst() {
+ ; CHECK-LABEL: name: agent_seq_cst
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 7, 7
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("agent") seq_cst
+ ret void
+}
+
+define amdgpu_kernel void @workgroup_acquire() {
+ ; CHECK-LABEL: name: workgroup_acquire
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 4, 8
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("workgroup") acquire
+ ret void
+}
+
+define amdgpu_kernel void @workgroup_release() {
+ ; CHECK-LABEL: name: workgroup_release
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 5, 8
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("workgroup") release
+ ret void
+}
+
+define amdgpu_kernel void @workgroup_acq_rel() {
+ ; CHECK-LABEL: name: workgroup_acq_rel
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 6, 8
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("workgroup") acq_rel
+ ret void
+}
+
+define amdgpu_kernel void @workgroup_seq_cst() {
+ ; CHECK-LABEL: name: workgroup_seq_cst
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 7, 8
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("workgroup") seq_cst
+ ret void
+}
+
+define amdgpu_kernel void @wavefront_acquire() {
+ ; CHECK-LABEL: name: wavefront_acquire
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 4, 9
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("wavefront") acquire
+ ret void
+}
+
+define amdgpu_kernel void @wavefront_release() {
+ ; CHECK-LABEL: name: wavefront_release
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 5, 9
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("wavefront") release
+ ret void
+}
+
+define amdgpu_kernel void @wavefront_acq_rel() {
+ ; CHECK-LABEL: name: wavefront_acq_rel
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 6, 9
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("wavefront") acq_rel
+ ret void
+}
+
+define amdgpu_kernel void @wavefront_seq_cst() {
+ ; CHECK-LABEL: name: wavefront_seq_cst
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: G_FENCE 7, 9
+ ; CHECK: S_ENDPGM 0
+ fence syncscope("wavefront") seq_cst
+ ret void
+}
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