[PATCH] D64069: [ARM] Add sign and zero extend patterns for MVE

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: t.p.northover, simon_tatham, SjoerdMeijer, samparker, ostannard.
Herald added subscribers: hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

The vmovlb instructions can be uses to sign or zero extend registers from one size to another. This adds some patterns for them and relevant testing. The VBICIMM generation is also put behind a hasNEON check (as is already done for VORRIMM).

Code originally by David Sherwood.


https://reviews.llvm.org/D64069

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/test/CodeGen/Thumb2/mve-sext.ll

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