[llvm] r364830 - AMDGPU/GlobalISel: Lower SALU min/max to cmp+select
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 1 11:30:46 PDT 2019
Author: arsenm
Date: Mon Jul 1 11:30:45 2019
New Revision: 364830
URL: http://llvm.org/viewvc/llvm-project?rev=364830&view=rev
Log:
AMDGPU/GlobalISel: Lower SALU min/max to cmp+select
Use a change observer to apply a register bank to the newly created
intermediate result register.
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=364830&r1=364829&r2=364830&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Mon Jul 1 11:30:45 2019
@@ -439,6 +439,22 @@ AMDGPURegisterBankInfo::getInstrAlternat
return AltMappings;
}
+ case TargetOpcode::G_SMIN:
+ case TargetOpcode::G_SMAX:
+ case TargetOpcode::G_UMIN:
+ case TargetOpcode::G_UMAX: {
+ static const OpRegBankEntry<3> Table[4] = {
+ { { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, 1 },
+ { { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, 1 },
+ { { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID }, 1 },
+
+ // Scalar requires cmp+select
+ { { AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID }, 2 }
+ };
+
+ const std::array<unsigned, 3> RegSrcOpIdx = { { 0, 1, 2 } };
+ return addMappingFromTable<3>(MI, MRI, RegSrcOpIdx, makeArrayRef(Table));
+ }
case TargetOpcode::G_UADDE:
case TargetOpcode::G_USUBE:
case TargetOpcode::G_SADDE:
@@ -1000,6 +1016,28 @@ void AMDGPURegisterBankInfo::applyMappin
llvm_unreachable("widen scalar should have succeeded");
return;
}
+ case AMDGPU::G_SMIN:
+ case AMDGPU::G_SMAX:
+ case AMDGPU::G_UMIN:
+ case AMDGPU::G_UMAX: {
+ Register DstReg = MI.getOperand(0).getReg();
+ const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI);
+ if (DstBank == &AMDGPU::VGPRRegBank)
+ break;
+
+ MachineFunction *MF = MI.getParent()->getParent();
+ MachineIRBuilder B(MI);
+ ApplySALUMapping ApplySALU(MRI);
+ GISelObserverWrapper Observer(&ApplySALU);
+ LegalizerHelper Helper(*MF, Observer, B);
+
+ // Turn scalar min/max into a compare and select.
+ LLT DstTy = MRI.getType(DstReg);
+ if (Helper.lower(MI, 0, DstTy) != LegalizerHelper::Legalized)
+ llvm_unreachable("lower should have succeeded");
+
+ return;
+ }
case AMDGPU::G_SEXT:
case AMDGPU::G_ZEXT: {
Register SrcReg = MI.getOperand(1).getReg();
@@ -1441,16 +1479,13 @@ AMDGPURegisterBankInfo::getInstrMapping(
case AMDGPU::G_SSUBE:
case AMDGPU::G_UMULH:
case AMDGPU::G_SMULH:
- if (isSALUMapping(MI))
- return getDefaultMappingSOP(MI);
- LLVM_FALLTHROUGH;
-
case AMDGPU::G_SMIN:
case AMDGPU::G_SMAX:
case AMDGPU::G_UMIN:
case AMDGPU::G_UMAX:
- // TODO: min/max can be scalar, but requires expanding as a compare and
- // select.
+ if (isSALUMapping(MI))
+ return getDefaultMappingSOP(MI);
+ LLVM_FALLTHROUGH;
case AMDGPU::G_FADD:
case AMDGPU::G_FSUB:
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir?rev=364830&r1=364829&r2=364830&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir Mon Jul 1 11:30:45 2019
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s
---
name: smax_ss
@@ -10,11 +10,16 @@ body: |
bb.0:
liveins: $sgpr0, $sgpr1
- ; CHECK-LABEL: name: smax_ss
- ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[SMAX:%[0-9]+]]:vgpr(s32) = G_SMAX [[COPY]], [[COPY2]]
+ ; FAST-LABEL: name: smax_ss
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
+ ; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
+ ; GREEDY-LABEL: name: smax_ss
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
+ ; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_SMAX %0, %1
@@ -28,10 +33,14 @@ body: |
bb.0:
liveins: $sgpr0, $vgpr0
- ; CHECK-LABEL: name: smax_sv
- ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK: [[SMAX:%[0-9]+]]:vgpr(s32) = G_SMAX [[COPY]], [[COPY1]]
+ ; FAST-LABEL: name: smax_sv
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[SMAX:%[0-9]+]]:vgpr(s32) = G_SMAX [[COPY]], [[COPY1]]
+ ; GREEDY-LABEL: name: smax_sv
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[SMAX:%[0-9]+]]:vgpr(s32) = G_SMAX [[COPY]], [[COPY1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0
%2:_(s32) = G_SMAX %0, %1
@@ -45,11 +54,15 @@ body: |
bb.0:
liveins: $sgpr0, $vgpr0
- ; CHECK-LABEL: name: smax_vs
- ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[SMAX:%[0-9]+]]:vgpr(s32) = G_SMAX [[COPY]], [[COPY2]]
+ ; FAST-LABEL: name: smax_vs
+ ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; FAST: [[SMAX:%[0-9]+]]:vgpr(s32) = G_SMAX [[COPY]], [[COPY2]]
+ ; GREEDY-LABEL: name: smax_vs
+ ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[SMAX:%[0-9]+]]:vgpr(s32) = G_SMAX [[COPY]], [[COPY1]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0
%2:_(s32) = G_SMAX %0, %1
@@ -63,11 +76,42 @@ body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; CHECK-LABEL: name: smax_vv
- ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
- ; CHECK: [[SMAX:%[0-9]+]]:vgpr(s32) = G_SMAX [[COPY]], [[COPY1]]
+ ; FAST-LABEL: name: smax_vv
+ ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; FAST: [[SMAX:%[0-9]+]]:vgpr(s32) = G_SMAX [[COPY]], [[COPY1]]
+ ; GREEDY-LABEL: name: smax_vv
+ ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; GREEDY: [[SMAX:%[0-9]+]]:vgpr(s32) = G_SMAX [[COPY]], [[COPY1]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_SMAX %0, %1
...
+
+# FIXME: This should use VGPR instruction
+---
+name: smax_ss_vgpr_use
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+
+ ; FAST-LABEL: name: smax_ss_vgpr_use
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
+ ; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
+ ; FAST: $vgpr0 = COPY [[SELECT]](s32)
+ ; GREEDY-LABEL: name: smax_ss_vgpr_use
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
+ ; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
+ ; GREEDY: $vgpr0 = COPY [[SELECT]](s32)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = G_SMAX %0, %1
+ $vgpr0 = COPY %2
+...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir?rev=364830&r1=364829&r2=364830&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir Mon Jul 1 11:30:45 2019
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s
---
name: smin_ss
@@ -10,11 +10,16 @@ body: |
bb.0:
liveins: $sgpr0, $sgpr1
- ; CHECK-LABEL: name: smin_ss
- ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[SMIN:%[0-9]+]]:vgpr(s32) = G_SMIN [[COPY]], [[COPY2]]
+ ; FAST-LABEL: name: smin_ss
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
+ ; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
+ ; GREEDY-LABEL: name: smin_ss
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
+ ; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_SMIN %0, %1
@@ -28,10 +33,14 @@ body: |
bb.0:
liveins: $sgpr0, $vgpr0
- ; CHECK-LABEL: name: smin_sv
- ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK: [[SMIN:%[0-9]+]]:vgpr(s32) = G_SMIN [[COPY]], [[COPY1]]
+ ; FAST-LABEL: name: smin_sv
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[SMIN:%[0-9]+]]:vgpr(s32) = G_SMIN [[COPY]], [[COPY1]]
+ ; GREEDY-LABEL: name: smin_sv
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[SMIN:%[0-9]+]]:vgpr(s32) = G_SMIN [[COPY]], [[COPY1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0
%2:_(s32) = G_SMIN %0, %1
@@ -45,11 +54,15 @@ body: |
bb.0:
liveins: $sgpr0, $vgpr0
- ; CHECK-LABEL: name: smin_vs
- ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[SMIN:%[0-9]+]]:vgpr(s32) = G_SMIN [[COPY]], [[COPY2]]
+ ; FAST-LABEL: name: smin_vs
+ ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; FAST: [[SMIN:%[0-9]+]]:vgpr(s32) = G_SMIN [[COPY]], [[COPY2]]
+ ; GREEDY-LABEL: name: smin_vs
+ ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[SMIN:%[0-9]+]]:vgpr(s32) = G_SMIN [[COPY]], [[COPY1]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0
%2:_(s32) = G_SMIN %0, %1
@@ -63,11 +76,42 @@ body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; CHECK-LABEL: name: smin_vv
- ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
- ; CHECK: [[SMIN:%[0-9]+]]:vgpr(s32) = G_SMIN [[COPY]], [[COPY1]]
+ ; FAST-LABEL: name: smin_vv
+ ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; FAST: [[SMIN:%[0-9]+]]:vgpr(s32) = G_SMIN [[COPY]], [[COPY1]]
+ ; GREEDY-LABEL: name: smin_vv
+ ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; GREEDY: [[SMIN:%[0-9]+]]:vgpr(s32) = G_SMIN [[COPY]], [[COPY1]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_SMIN %0, %1
...
+
+# FIXME: This should use VGPR instruction
+---
+name: smin_ss_vgpr_use
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+
+ ; FAST-LABEL: name: smin_ss_vgpr_use
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
+ ; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
+ ; FAST: $vgpr0 = COPY [[SELECT]](s32)
+ ; GREEDY-LABEL: name: smin_ss_vgpr_use
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
+ ; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
+ ; GREEDY: $vgpr0 = COPY [[SELECT]](s32)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = G_SMIN %0, %1
+ $vgpr0 = COPY %2
+...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir?rev=364830&r1=364829&r2=364830&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir Mon Jul 1 11:30:45 2019
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s
---
name: umax_ss
@@ -10,11 +10,16 @@ body: |
bb.0:
liveins: $sgpr0, $sgpr1
- ; CHECK-LABEL: name: umax_ss
- ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[UMAX:%[0-9]+]]:vgpr(s32) = G_UMAX [[COPY]], [[COPY2]]
+ ; FAST-LABEL: name: umax_ss
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
+ ; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
+ ; GREEDY-LABEL: name: umax_ss
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
+ ; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_UMAX %0, %1
@@ -28,10 +33,14 @@ body: |
bb.0:
liveins: $sgpr0, $vgpr0
- ; CHECK-LABEL: name: umax_sv
- ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK: [[UMAX:%[0-9]+]]:vgpr(s32) = G_UMAX [[COPY]], [[COPY1]]
+ ; FAST-LABEL: name: umax_sv
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[UMAX:%[0-9]+]]:vgpr(s32) = G_UMAX [[COPY]], [[COPY1]]
+ ; GREEDY-LABEL: name: umax_sv
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[UMAX:%[0-9]+]]:vgpr(s32) = G_UMAX [[COPY]], [[COPY1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0
%2:_(s32) = G_UMAX %0, %1
@@ -45,11 +54,15 @@ body: |
bb.0:
liveins: $sgpr0, $vgpr0
- ; CHECK-LABEL: name: umax_vs
- ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[UMAX:%[0-9]+]]:vgpr(s32) = G_UMAX [[COPY]], [[COPY2]]
+ ; FAST-LABEL: name: umax_vs
+ ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; FAST: [[UMAX:%[0-9]+]]:vgpr(s32) = G_UMAX [[COPY]], [[COPY2]]
+ ; GREEDY-LABEL: name: umax_vs
+ ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[UMAX:%[0-9]+]]:vgpr(s32) = G_UMAX [[COPY]], [[COPY1]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0
%2:_(s32) = G_UMAX %0, %1
@@ -63,11 +76,42 @@ body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; CHECK-LABEL: name: umax_vv
- ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
- ; CHECK: [[UMAX:%[0-9]+]]:vgpr(s32) = G_UMAX [[COPY]], [[COPY1]]
+ ; FAST-LABEL: name: umax_vv
+ ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; FAST: [[UMAX:%[0-9]+]]:vgpr(s32) = G_UMAX [[COPY]], [[COPY1]]
+ ; GREEDY-LABEL: name: umax_vv
+ ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; GREEDY: [[UMAX:%[0-9]+]]:vgpr(s32) = G_UMAX [[COPY]], [[COPY1]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_UMAX %0, %1
...
+
+# FIXME: This should use VGPR instruction
+---
+name: umax_ss_vgpr_use
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+
+ ; FAST-LABEL: name: umax_ss_vgpr_use
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
+ ; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
+ ; FAST: $vgpr0 = COPY [[SELECT]](s32)
+ ; GREEDY-LABEL: name: umax_ss_vgpr_use
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
+ ; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
+ ; GREEDY: $vgpr0 = COPY [[SELECT]](s32)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = G_UMAX %0, %1
+ $vgpr0 = COPY %2
+...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir?rev=364830&r1=364829&r2=364830&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir Mon Jul 1 11:30:45 2019
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s
---
name: umin_ss
@@ -10,11 +10,16 @@ body: |
bb.0:
liveins: $sgpr0, $sgpr1
- ; CHECK-LABEL: name: umin_ss
- ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[UMIN:%[0-9]+]]:vgpr(s32) = G_UMIN [[COPY]], [[COPY2]]
+ ; FAST-LABEL: name: umin_ss
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
+ ; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
+ ; GREEDY-LABEL: name: umin_ss
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
+ ; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_UMIN %0, %1
@@ -28,10 +33,14 @@ body: |
bb.0:
liveins: $sgpr0, $vgpr0
- ; CHECK-LABEL: name: umin_sv
- ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK: [[UMIN:%[0-9]+]]:vgpr(s32) = G_UMIN [[COPY]], [[COPY1]]
+ ; FAST-LABEL: name: umin_sv
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[UMIN:%[0-9]+]]:vgpr(s32) = G_UMIN [[COPY]], [[COPY1]]
+ ; GREEDY-LABEL: name: umin_sv
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[UMIN:%[0-9]+]]:vgpr(s32) = G_UMIN [[COPY]], [[COPY1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0
%2:_(s32) = G_UMIN %0, %1
@@ -45,11 +54,15 @@ body: |
bb.0:
liveins: $sgpr0, $vgpr0
- ; CHECK-LABEL: name: umin_vs
- ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[UMIN:%[0-9]+]]:vgpr(s32) = G_UMIN [[COPY]], [[COPY2]]
+ ; FAST-LABEL: name: umin_vs
+ ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; FAST: [[UMIN:%[0-9]+]]:vgpr(s32) = G_UMIN [[COPY]], [[COPY2]]
+ ; GREEDY-LABEL: name: umin_vs
+ ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[UMIN:%[0-9]+]]:vgpr(s32) = G_UMIN [[COPY]], [[COPY1]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0
%2:_(s32) = G_UMIN %0, %1
@@ -63,11 +76,42 @@ body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; CHECK-LABEL: name: umin_vv
- ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
- ; CHECK: [[UMIN:%[0-9]+]]:vgpr(s32) = G_UMIN [[COPY]], [[COPY1]]
+ ; FAST-LABEL: name: umin_vv
+ ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; FAST: [[UMIN:%[0-9]+]]:vgpr(s32) = G_UMIN [[COPY]], [[COPY1]]
+ ; GREEDY-LABEL: name: umin_vv
+ ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; GREEDY: [[UMIN:%[0-9]+]]:vgpr(s32) = G_UMIN [[COPY]], [[COPY1]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_UMIN %0, %1
...
+
+# FIXME: This should use VGPR instruction
+---
+name: umin_ss_vgpr_use
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+
+ ; FAST-LABEL: name: umin_ss_vgpr_use
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
+ ; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
+ ; FAST: $vgpr0 = COPY [[SELECT]](s32)
+ ; GREEDY-LABEL: name: umin_ss_vgpr_use
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
+ ; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
+ ; GREEDY: $vgpr0 = COPY [[SELECT]](s32)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = G_UMIN %0, %1
+ $vgpr0 = COPY %2
+...
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