[llvm] r364807 - AMDGPU/GlobalISel: Fail instead of assert when selecting loads

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Mon Jul  1 09:36:39 2019
New Revision: 364807

URL: http://llvm.org/viewvc/llvm-project?rev=364807&view=rev
Log:
AMDGPU/GlobalISel: Fail instead of assert when selecting loads

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp?rev=364807&r1=364806&r2=364807&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp Mon Jul  1 09:36:39 2019
@@ -1036,25 +1036,31 @@ bool AMDGPUInstructionSelector::selectG_
   MachineBasicBlock *BB = I.getParent();
   MachineFunction *MF = BB->getParent();
   MachineRegisterInfo &MRI = MF->getRegInfo();
-  DebugLoc DL = I.getDebugLoc();
-  unsigned DstReg = I.getOperand(0).getReg();
-  unsigned PtrReg = I.getOperand(1).getReg();
+  const DebugLoc &DL = I.getDebugLoc();
+  Register DstReg = I.getOperand(0).getReg();
+  Register PtrReg = I.getOperand(1).getReg();
   unsigned LoadSize = RBI.getSizeInBits(DstReg, MRI, TRI);
   unsigned Opcode;
 
+  if (MRI.getType(I.getOperand(1).getReg()).getSizeInBits() == 32) {
+    LLVM_DEBUG(dbgs() << "Unhandled address space\n");
+    return false;
+  }
+
   SmallVector<GEPInfo, 4> AddrInfo;
 
   getAddrModeInfo(I, MRI, AddrInfo);
 
   switch (LoadSize) {
-  default:
-    llvm_unreachable("Load size not supported\n");
   case 32:
     Opcode = AMDGPU::FLAT_LOAD_DWORD;
     break;
   case 64:
     Opcode = AMDGPU::FLAT_LOAD_DWORDX2;
     break;
+  default:
+    LLVM_DEBUG(dbgs() << "Unhandled load size\n");
+    return false;
   }
 
   MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(Opcode))