[PATCH] D63452: AMDGPU: Support some GDS atomics
Nicolai Hähnle via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 1 09:16:36 PDT 2019
nhaehnle marked 8 inline comments as done.
nhaehnle added inline comments.
================
Comment at: lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:137
const LLT LocalPtr = GetAddrSpacePtr(AMDGPUAS::LOCAL_ADDRESS);
+ const LLT RegionPtr = GetAddrSpacePtr(AMDGPUAS::REGION_ADDRESS);
const LLT FlatPtr = GetAddrSpacePtr(AMDGPUAS::FLAT_ADDRESS);
----------------
arsenm wrote:
> Probably should drop the global isel changes for now. I have a large patch replacing the load and store handling
Sure, dropping this.
================
Comment at: lib/Target/AMDGPU/DSInstructions.td:604
-class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
+class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds> : GCNPat <
(vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
----------------
arsenm wrote:
> This can default to 0 instead of touching all the other patterns?
Sure.
================
Comment at: lib/Target/AMDGPU/SIMachineFunctionInfo.cpp:50
+ HighBitsOf32BitAddress(0),
+ GDSSize(4096) {
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
----------------
arsenm wrote:
> Why is this not defaulting to 0?
Yeah, presumably it should. I'm changing it.
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D63452/new/
https://reviews.llvm.org/D63452
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