[PATCH] D64009: [ARM] MVE: support QQPRRegClass and QQQQPRRegClass
Simon Tatham via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 1 08:56:19 PDT 2019
simon_tatham accepted this revision.
simon_tatham added a comment.
This revision is now accepted and ready to land.
Otherwise LGTM.
================
Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:1568
// v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
- // load / store 4 to 8 consecutive D registers.
- if (Subtarget->hasNEON()) {
+ // load / store 4 to 8 consecutive NEON D registers or MVE Q registers.
+ if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
----------------
Comment nitpick: 4 to 8 consecutive NEON D registers, or 2 to 4 consecutive MVE Q registers.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D64009/new/
https://reviews.llvm.org/D64009
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