[llvm] r364784 - AMDGPU/GlobalISel: Tolerate copies with no type set

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Mon Jul  1 08:23:04 2019
New Revision: 364784

URL: http://llvm.org/viewvc/llvm-project?rev=364784&view=rev
Log:
AMDGPU/GlobalISel: Tolerate copies with no type set

isVCC has the same bug, but isn't used in a context where it can cause
a problem.

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp?rev=364784&r1=364783&r2=364784&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp Mon Jul  1 08:23:04 2019
@@ -65,9 +65,12 @@ static bool isSCC(unsigned Reg, const Ma
   auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
   const TargetRegisterClass *RC =
       RegClassOrBank.dyn_cast<const TargetRegisterClass*>();
-  if (RC)
-    return RC->getID() == AMDGPU::SReg_32_XM0RegClassID &&
-           MRI.getType(Reg).getSizeInBits() == 1;
+  if (RC) {
+    if (RC->getID() != AMDGPU::SReg_32_XM0RegClassID)
+      return false;
+    const LLT Ty = MRI.getType(Reg);
+    return Ty.isValid() && Ty.getSizeInBits() == 1;
+  }
 
   const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
   return RB->getID() == AMDGPU::SCCRegBankID;

Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir?rev=364784&r1=364783&r2=364784&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir Mon Jul  1 08:23:04 2019
@@ -138,3 +138,59 @@ body: |
     %5:vgpr(s32) = G_SELECT %3, %1, %2
     G_STORE %5, %0 :: (store 4, addrspace 1)
 ...
+---
+
+name:            copy_sgpr_no_type
+legalized:       true
+regBankSelected: true
+
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; GCN-LABEL: name: copy_sgpr_no_type
+    ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; GCN: S_ENDPGM 0, implicit [[COPY]]
+    %0:sreg_32_xm0 = COPY $sgpr0
+    %1:sreg_32_xm0 = COPY %0
+    S_ENDPGM 0, implicit %1
+
+...
+
+---
+
+name:            copy_vgpr_no_type
+legalized:       true
+regBankSelected: true
+
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; GCN-LABEL: name: copy_vgpr_no_type
+    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: S_ENDPGM 0, implicit [[COPY]]
+    %0:vgpr_32 = COPY $vgpr0
+    %1:vgpr_32 = COPY %0
+    S_ENDPGM 0, implicit %1
+
+...
+
+---
+
+name:            copy_maybe_vcc
+legalized:       true
+regBankSelected: true
+
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+    ; GCN-LABEL: name: copy_maybe_vcc
+    ; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+    ; GCN: S_ENDPGM 0, implicit [[COPY]]
+    %0:sreg_64_xexec = COPY $sgpr0_sgpr1
+    %1:sreg_64_xexec  = COPY %0
+    S_ENDPGM 0, implicit %1
+
+...