[llvm] r364762 - AMDGPU/GlobalISel: Use vcc reg bank for amdgcn.wqm.vote
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 1 06:30:09 PDT 2019
Author: arsenm
Date: Mon Jul 1 06:30:09 2019
New Revision: 364762
URL: http://llvm.org/viewvc/llvm-project?rev=364762&view=rev
Log:
AMDGPU/GlobalISel: Use vcc reg bank for amdgcn.wqm.vote
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
- copied, changed from r364761, llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-wqm-vote.mir
Removed:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-wqm-vote.mir
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=364762&r1=364761&r2=364762&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Mon Jul 1 06:30:09 2019
@@ -1521,7 +1521,7 @@ AMDGPURegisterBankInfo::getInstrMapping(
case Intrinsic::amdgcn_wqm_vote: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
OpdsMapping[0] = OpdsMapping[2]
- = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
+ = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size);
break;
}
case Intrinsic::amdgcn_s_buffer_load: {
Removed: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-wqm-vote.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-wqm-vote.mir?rev=364761&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-wqm-vote.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-wqm-vote.mir (removed)
@@ -1,57 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
-
----
-name: wqm_vote_scc
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0, $sgpr1
- ; CHECK-LABEL: name: wqm_vote_scc
- ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
- ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
- ; CHECK: [[INT:%[0-9]+]]:sgpr(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), [[COPY2]](s1)
- %0:_(s32) = COPY $sgpr0
- %1:_(s32) = COPY $sgpr1
- %2:_(s1) = G_ICMP intpred(ne), %0, %1
- %3:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), %2
-...
-
----
-name: wqm_vote_vcc
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0, $vgpr1
- ; CHECK-LABEL: name: wqm_vote_vcc
- ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
- ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
- ; CHECK: [[INT:%[0-9]+]]:sgpr(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), [[COPY2]](s1)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s1) = G_ICMP intpred(ne), %0, %1
- %3:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), %2
-...
-
----
-name: wqm_vote_sgpr
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0, $sgpr1
- ; CHECK-LABEL: name: wqm_vote_sgpr
- ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[INT:%[0-9]+]]:sgpr(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), [[TRUNC]](s1)
- %0:_(s32) = COPY $sgpr0
- %1:_(s1) = G_TRUNC %0
- %2:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), %1
-...
Copied: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir (from r364761, llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-wqm-vote.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir?p2=llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir&p1=llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-wqm-vote.mir&r1=364761&r2=364762&rev=364762&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-wqm-vote.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir Mon Jul 1 06:30:09 2019
@@ -13,8 +13,8 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
- ; CHECK: [[INT:%[0-9]+]]:sgpr(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), [[COPY2]](s1)
+ ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
+ ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), [[COPY2]](s1)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
@@ -32,8 +32,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
- ; CHECK: [[INT:%[0-9]+]]:sgpr(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), [[COPY2]](s1)
+ ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), [[ICMP]](s1)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
@@ -50,7 +49,8 @@ body: |
; CHECK-LABEL: name: wqm_vote_sgpr
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[INT:%[0-9]+]]:sgpr(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), [[TRUNC]](s1)
+ ; CHECK: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+ ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), [[COPY1]](s1)
%0:_(s32) = COPY $sgpr0
%1:_(s1) = G_TRUNC %0
%2:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), %1
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