[PATCH] D63938: [ARM] Stop using scalar FP instructions in integer-only MVE mode.

Sun Jun 30 12:46:19 PDT 2019

dmgreen added a comment.

I still can't say I'm totally convinced by this way of using addRegisterClass for everything and then trying to stop the compiler from ever using them. When would we want to use a floating point load, for example? But I'm not sure enough about what a sensible alternative would be, so lets at least try it and see. This certainly fixes thing. If it does keep causing headaches we can always change it later!

Can you add a test that does some MVE expansion of floating point operations, for floats and halfs. Just a simple "fadd" using +mve should be fine to show things are working.

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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:605
     addRegisterClass(MVT::f32, &ARM::SPRRegClass);
     addRegisterClass(MVT::f64, &ARM::DPRRegClass);
+    if (!Subtarget->hasVFP2Base()) {
----------------
Should this be behind hasFPRegs64 instead?

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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:617

   if (Subtarget->hasFullFP16()) {
     addRegisterClass(MVT::f16, &ARM::HPRRegClass);
----------------
How come we don't have to do the same for fullfp16 to work?

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Comment at: llvm/test/CodeGen/ARM/fp16-instructions.ll:5
+; RUN: llc < %s -mtriple=thumbv8.1m-none-eabi -mattr=+mve | FileCheck %s --check-prefixes=CHECK,CHECK-SOFT
+; RUN: llc < %s -mtriple=thumbv8.1m-none-eabi -float-abi=soft -mattr=+mve | FileCheck %s --check-prefixes=CHECK,CHECK-SOFT

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These should be thumbv8.1m.main-none-eabi

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Comment at: llvm/test/CodeGen/Thumb2/float-ops.ll:268
+; ONLYREGS: lsls    r2, r2, #31
+; ONLYREGS: vmovne.f32      s2, s0
 ; HARD: lsls    r0, r0, #31
----------------
This is worse than before by the looks of it? We move things into fp registers just to move them out again.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63938/new/

https://reviews.llvm.org/D63938