[PATCH] D55570: [AMDGPU] Improve SDWA generation for V_OR_B32_E32.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: test/CodeGen/AMDGPU/sdwa-ors.mir:4-11
+# GCN-LABEL: {{^}}name: sdwa_test
+# GFX9: V_OR_B32_sdwa 0, %{{[0-9]+}}, 0, killed %{{[0-9]+}}, 0, 6, 0, 2, 6, implicit $exec
+# GFX9: V_OR_B32_sdwa 0, %{{[0-9]+}}, 0, killed %{{[0-9]+}}, 0, 6, 0, 1, 6, implicit $exec
+# GFX9: V_OR_B32_sdwa 0, %{{[0-9]+}}, 0, killed %{{[0-9]+}}, 0, 6, 0, 0, 6, implicit $exec
+# GFX9: V_OR_B32_sdwa 0, %{{[0-9]+}}, 0, killed %{{[0-9]+}}, 0, 6, 0, 3, 6, implicit $exec
+# GFX9: V_OR_B32_sdwa 0, %{{[0-9]+}}, 0, killed %{{[0-9]+}}, 0, 6, 0, 5, 6, implicit $exec
+# GFX9: V_OR_B32_sdwa 0, %{{[0-9]+}}, 0, killed %{{[0-9]+}}, 0, 6, 0, 4, 6, implicit $exec
----------------
Can probably use update_mir_test_checks for this one


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Comment at: test/CodeGen/AMDGPU/sdwa-ors.mir:35
+    %16:vgpr_32 = V_OR_B32_e64 killed %15, killed %13, implicit $exec
+    GLOBAL_STORE_DWORD %2, %16, 0, 0, 0, implicit $exec :: (volatile store 4, addrspace 1)
+
----------------
Can you condense the register values for this? Running -run-pass=none with -simplify-mir should work once you delete the registers section


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  https://reviews.llvm.org/D55570/new/

https://reviews.llvm.org/D55570