[PATCH] D61289: [globalisel] Add G_SEXT_INREG
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 28 12:46:57 PDT 2019
arsenm added a comment.
I'm running into a related problem attempting to implement narrowScalar for G_SEXT. AMDGPU is allergic to 64-bit shifts, so I want to implement
%1:_(s32) = G_TRUNC %0
%2:_(s64).= G_SEXT %1
As
%1:_(s32) = G_TRUNC %0
%2:_(s32) = G_ASHR %1, 31
%3:_:(s64) = G_MERGE_VALUES %1, %2
Since the 64-bit shift is possible, the artifact combiner produces the undesirable 64-bit shift combination. Worse, this combination ends up infinitely looping if the required shift requires legalizatiion
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D61289/new/
https://reviews.llvm.org/D61289
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