[llvm] r364512 - [GlobalISel] Accept multiple vregs for lowerCall's args
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 28 01:29:43 PDT 2019
Thanks, I'll investigate!
On Thu, 27 Jun 2019 at 18:48, Alexander Kornienko <alexfh at google.com> wrote:
>
> This revision seems to be causing a test failure (llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll) under ASAN. It may also be one of the related patches you checked in today, but this one looks most suspicious to me. Please fix or revert. Thanks!
>
> ASAN logs:
> =================================================================
> ==7505==ERROR: AddressSanitizer: stack-use-after-scope on address 0x7f2d86b01d20 at pc 0x55a3523bfeba bp 0x7ffc4b0153c0 sp 0x7ffc4b014b88
> READ of size 4 at 0x7f2d86b01d20 thread T0
> #0 0x55a3523bfeb9 in __asan_memcpy llvm/projects/compiler-rt/lib/asan/asan_interceptors_memintrinsics.cc:22:3
> #1 0x55a3527f785c in void llvm::SmallVectorTemplateBase<llvm::Register, true>::uninitialized_copy<llvm::Register const, llvm::Register>(llvm::Register const*, llvm::Register const*, llvm::Register*, std::__g::enable_if<std::is_same<std::__g::remove_const<llvm::Register const>::type, llvm::Register>::value, void>::type*) llvm/include/llvm/ADT/SmallVector.h:294:7
> #2 0x55a3527f76bb in void llvm::SmallVectorImpl<llvm::Register>::append<llvm::Register const*, void>(llvm::Register const*, llvm::Register const*) llvm/include/llvm/ADT/SmallVector.h:392:5
> #3 0x55a3527f660b in llvm::CallLowering::ArgInfo::ArgInfo(llvm::ArrayRef<llvm::Register>, llvm::Type*, llvm::ISD::ArgFlagsTy, bool) llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h:53:11
> #4 0x55a35400ebcb in llvm::CallLowering::lowerCall(llvm::MachineIRBuilder&, llvm::ImmutableCallSite, llvm::ArrayRef<llvm::Register>, llvm::ArrayRef<llvm::ArrayRef<llvm::Register> >, llvm::Register, std::__g::function<unsigned int ()>) const llvm/lib/CodeGen/GlobalISel/CallLowering.cpp:44:13
> #5 0x55a354032f07 in llvm::IRTranslator::translateCall(llvm::User const&, llvm::MachineIRBuilder&) llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp:1580:14
> #6 0x55a35403932a in llvm::IRTranslator::translate(llvm::Instruction const&) llvm/include/llvm/IR/Instruction.def:209:1
> #7 0x55a35403abd9 in llvm::IRTranslator::runOnMachineFunction(llvm::MachineFunction&) llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp:2298:13
> #8 0x55a3543bd8d8 in llvm::MachineFunctionPass::runOnFunction(llvm::Function&) llvm/lib/CodeGen/MachineFunctionPass.cpp:73:13
> #9 0x55a35685c158 in llvm::FPPassManager::runOnFunction(llvm::Function&) llvm/lib/IR/LegacyPassManager.cpp:1648:27
> #10 0x55a35685c5f2 in llvm::FPPassManager::runOnModule(llvm::Module&) llvm/lib/IR/LegacyPassManager.cpp:1685:16
> #11 0x55a35685cf68 in (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) llvm/lib/IR/LegacyPassManager.cpp:1752:27
> #12 0x55a35685c915 in llvm::legacy::PassManagerImpl::run(llvm::Module&) llvm/lib/IR/LegacyPassManager.cpp:1865:44
> #13 0x55a3523dbfa9 in compileModule(char**, llvm::LLVMContext&) llvm/tools/llc/llc.cpp:601:8
> #14 0x55a3523d9e4f in main llvm/tools/llc/llc.cpp:355:22
> ...
>
> Address 0x7f2d86b01d20 is located in stack of thread T0 at offset 288 in frame
> #0 0x55a3540321cf in llvm::IRTranslator::translateCall(llvm::User const&, llvm::MachineIRBuilder&) llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp:1540
>
> This frame has 19 object(s):
> [32, 176) 'Args' (line 1562)
> [240, 244) 'SwiftErrorVReg' (line 1563)
> [256, 272) 'ref.tmp' (line 1564)
> [288, 292) 'InVReg' (line 1567) <== Memory access at offset 288 is inside this variable
> [304, 320) 'agg.tmp43'
> [336, 352) 'ref.tmp47' (line 1568)
> [368, 392) 'ref.tmp50' (line 1568)
> [432, 448) 'ref.tmp58' (line 1570)
> [464, 480) 'ref.tmp66' (line 1575)
> [496, 504) 'agg.tmp76'
> [528, 544) 'agg.tmp78'
> [560, 592) 'agg.tmp80'
> [624, 640) 'ResultRegs' (line 1591)
> [656, 672) 'MIB' (line 1597)
> [688, 704) 'ref.tmp112' (line 1602)
> [720, 736) 'VRegs' (line 1606)
> [752, 800) 'Info' (line 1614)
> [832, 856) 'agg.tmp167'
> [896, 920) 'ref.tmp174' (line 1622)
>
> On Thu, Jun 27, 2019 at 11:18 AM Diana Picus via llvm-commits <llvm-commits at lists.llvm.org> wrote:
>>
>> Author: rovka
>> Date: Thu Jun 27 02:18:03 2019
>> New Revision: 364512
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=364512&view=rev
>> Log:
>> [GlobalISel] Accept multiple vregs for lowerCall's args
>>
>> Change the interface of CallLowering::lowerCall to accept several
>> virtual registers for each argument, instead of just one. This is a
>> follow-up to D46018.
>>
>> CallLowering::lowerReturn was similarly refactored in D49660 and
>> lowerFormalArguments in D63549.
>>
>> With this change, we no longer pack the virtual registers generated for
>> aggregates into one big lump before delegating to the target. Therefore,
>> the target can decide itself whether it wants to handle them as separate
>> pieces or use one big register.
>>
>> ARM and AArch64 have been updated to use the passed in virtual registers
>> directly, which means we no longer need to generate so many
>> merge/extract instructions.
>>
>> NFCI for AMDGPU, Mips and X86.
>>
>> Differential Revision: https://reviews.llvm.org/D63551
>>
>> Modified:
>> llvm/trunk/include/llvm/CodeGen/GlobalISel/CallLowering.h
>> llvm/trunk/lib/CodeGen/GlobalISel/CallLowering.cpp
>> llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
>> llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp
>> llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp
>> llvm/trunk/lib/Target/X86/X86CallLowering.cpp
>> llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll
>> llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
>> llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll
>> llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
>>
>> Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/CallLowering.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/CallLowering.h?rev=364512&r1=364511&r2=364512&view=diff
>> ==============================================================================
>> --- llvm/trunk/include/llvm/CodeGen/GlobalISel/CallLowering.h (original)
>> +++ llvm/trunk/include/llvm/CodeGen/GlobalISel/CallLowering.h Thu Jun 27 02:18:03 2019
>> @@ -262,8 +262,10 @@ public:
>> /// stored (or 0 if there is no return value). There will be one register for
>> /// each non-aggregate type, as returned by \c computeValueLLTs.
>> ///
>> - /// \p ArgRegs is a list of virtual registers containing each argument that
>> - /// needs to be passed.
>> + /// \p ArgRegs is a list of lists of virtual registers containing each
>> + /// argument that needs to be passed (argument \c i should be placed in \c
>> + /// ArgRegs[i]). For each argument, there will be one register for each
>> + /// non-aggregate type, as returned by \c computeValueLLTs.
>> ///
>> /// \p SwiftErrorVReg is non-zero if the call has a swifterror inout
>> /// parameter, and contains the vreg that the swifterror should be copied into
>> @@ -276,8 +278,8 @@ public:
>> ///
>> /// \return true if the lowering succeeded, false otherwise.
>> bool lowerCall(MachineIRBuilder &MIRBuilder, ImmutableCallSite CS,
>> - ArrayRef<Register> ResRegs, ArrayRef<Register> ArgRegs,
>> - Register SwiftErrorVReg,
>> + ArrayRef<Register> ResRegs,
>> + ArrayRef<ArrayRef<Register>> ArgRegs, Register SwiftErrorVReg,
>> std::function<unsigned()> GetCalleeReg) const;
>> };
>>
>>
>> Modified: llvm/trunk/lib/CodeGen/GlobalISel/CallLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/CallLowering.cpp?rev=364512&r1=364511&r2=364512&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/GlobalISel/CallLowering.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/GlobalISel/CallLowering.cpp Thu Jun 27 02:18:03 2019
>> @@ -29,7 +29,7 @@ void CallLowering::anchor() {}
>>
>> bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, ImmutableCallSite CS,
>> ArrayRef<Register> ResRegs,
>> - ArrayRef<Register> ArgRegs,
>> + ArrayRef<ArrayRef<Register>> ArgRegs,
>> Register SwiftErrorVReg,
>> std::function<unsigned()> GetCalleeReg) const {
>> auto &DL = CS.getParent()->getParent()->getParent()->getDataLayout();
>>
>> Modified: llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp?rev=364512&r1=364511&r2=364512&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp Thu Jun 27 02:18:03 2019
>> @@ -1587,8 +1587,8 @@ bool IRTranslator::translateCall(const U
>> if (!F || !F->isIntrinsic() || ID == Intrinsic::not_intrinsic) {
>> ArrayRef<Register> Res = getOrCreateVRegs(CI);
>>
>> - SmallVector<Register, 8> Args;
>> - Register SwiftErrorVReg;
>> + SmallVector<ArrayRef<Register>, 8> Args;
>> + Register SwiftErrorVReg = 0;
>> for (auto &Arg: CI.arg_operands()) {
>> if (CLI->supportSwiftError() && isSwiftError(Arg)) {
>> LLT Ty = getLLTForType(*Arg->getType(), *DL);
>> @@ -1600,7 +1600,7 @@ bool IRTranslator::translateCall(const U
>> SwiftError.getOrCreateVRegDefAt(&CI, &MIRBuilder.getMBB(), Arg);
>> continue;
>> }
>> - Args.push_back(packRegs(*Arg, MIRBuilder));
>> + Args.push_back(getOrCreateVRegs(*Arg));
>> }
>>
>> MF->getFrameInfo().setHasCalls(true);
>> @@ -1684,7 +1684,7 @@ bool IRTranslator::translateInvoke(const
>> ArrayRef<Register> Res;
>> if (!I.getType()->isVoidTy())
>> Res = getOrCreateVRegs(I);
>> - SmallVector<Register, 8> Args;
>> + SmallVector<ArrayRef<Register>, 8> Args;
>> Register SwiftErrorVReg = 0;
>> for (auto &Arg : I.arg_operands()) {
>> if (CLI->supportSwiftError() && isSwiftError(Arg)) {
>> @@ -1698,7 +1698,7 @@ bool IRTranslator::translateInvoke(const
>> continue;
>> }
>>
>> - Args.push_back(packRegs(*Arg, MIRBuilder));
>> + Args.push_back(getOrCreateVRegs(*Arg));
>> }
>>
>> if (!CLI->lowerCall(MIRBuilder, &I, Res, Args, SwiftErrorVReg,
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp?rev=364512&r1=364511&r2=364512&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp Thu Jun 27 02:18:03 2019
>> @@ -441,10 +441,9 @@ bool AArch64CallLowering::lowerCall(Mach
>>
>> SmallVector<ArgInfo, 8> SplitArgs;
>> for (auto &OrigArg : OrigArgs) {
>> - assert(OrigArg.Regs.size() == 1 && "Can't handle multple regs yet");
>> splitToValueTypes(OrigArg, SplitArgs, DL, MRI, CallConv,
>> [&](Register Reg, uint64_t Offset) {
>> - MIRBuilder.buildExtract(Reg, OrigArg.Regs[0], Offset);
>> + llvm_unreachable("Call params should already be split");
>> });
>> // AAPCS requires that we zero-extend i1 to 8 bits by the caller.
>> if (OrigArg.Ty->isIntegerTy(1))
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp?rev=364512&r1=364511&r2=364512&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp Thu Jun 27 02:18:03 2019
>> @@ -596,14 +596,9 @@ bool ARMCallLowering::lowerCall(MachineI
>> if (Arg.Flags.isByVal())
>> return false;
>>
>> - assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
>> -
>> - SmallVector<Register, 8> Regs;
>> - splitToValueTypes(Arg, ArgInfos, MF,
>> - [&](unsigned Reg) { Regs.push_back(Reg); });
>> -
>> - if (Regs.size() > 1)
>> - MIRBuilder.buildUnmerge(Regs, Arg.Regs[0]);
>> + splitToValueTypes(Arg, ArgInfos, MF, [&](Register Reg) {
>> + llvm_unreachable("Function args should already be split");
>> + });
>> }
>>
>> auto ArgAssignFn = TLI.CCAssignFnForCall(CallConv, IsVarArg);
>>
>> Modified: llvm/trunk/lib/Target/X86/X86CallLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CallLowering.cpp?rev=364512&r1=364511&r2=364512&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86CallLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86CallLowering.cpp Thu Jun 27 02:18:03 2019
>> @@ -409,7 +409,9 @@ bool X86CallLowering::lowerCall(MachineI
>> if (OrigArg.Flags.isByVal())
>> return false;
>>
>> - assert(OrigArg.Regs.size() == 1 && "Can't handle multple regs yet");
>> + if (OrigArg.Regs.size() > 1)
>> + return false;
>> +
>> if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
>> [&](ArrayRef<Register> Regs) {
>> MIRBuilder.buildUnmerge(Regs, OrigArg.Regs[0]);
>>
>> Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll?rev=364512&r1=364511&r2=364512&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll (original)
>> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll Thu Jun 27 02:18:03 2019
>> @@ -7,20 +7,14 @@
>> ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[ADDR]], [[CST]](s64)
>> ; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 8 from %ir.ptr + 8)
>>
>> -; CHECK: [[IMPDEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
>> -; CHECK: [[INS1:%[0-9]+]]:_(s128) = G_INSERT [[IMPDEF]], [[LO]](s64), 0
>> -; CHECK: [[INS2:%[0-9]+]]:_(s128) = G_INSERT [[INS1]], [[HI]](s64), 64
>> -; CHECK: [[EXTLO:%[0-9]+]]:_(s64) = G_EXTRACT [[INS2]](s128), 0
>> -; CHECK: [[EXTHI:%[0-9]+]]:_(s64) = G_EXTRACT [[INS2]](s128), 64
>> -
>> ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
>> ; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
>> ; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST2]](s64)
>> -; CHECK: G_STORE [[EXTLO]](s64), [[GEP2]](p0) :: (store 8 into stack, align 1)
>> +; CHECK: G_STORE [[LO]](s64), [[GEP2]](p0) :: (store 8 into stack, align 1)
>> ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
>> ; CHECK: [[CST3:%[0-9]+]]:_(s64) = COPY [[CST]]
>> ; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST3]](s64)
>> -; CHECK: G_STORE [[EXTHI]](s64), [[GEP3]](p0) :: (store 8 into stack + 8, align 1)
>> +; CHECK: G_STORE [[HI]](s64), [[GEP3]](p0) :: (store 8 into stack + 8, align 1)
>> define void @test_split_struct([2 x i64]* %ptr) {
>> %struct = load [2 x i64], [2 x i64]* %ptr
>> call void @take_split_struct([2 x i64]* null, i64 1, i64 2, i64 3,
>>
>> Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll?rev=364512&r1=364511&r2=364512&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll (original)
>> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll Thu Jun 27 02:18:03 2019
>> @@ -59,21 +59,16 @@ define void @take_128bit_struct([2 x i64
>> ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
>> ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP %0, [[CST]](s64)
>> ; CHECK: [[LD2:%[0-9]+]]:_(s64) = G_LOAD %3(p0) :: (load 8 from %ir.ptr + 8)
>> -; CHECK: [[IMPDEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
>> -; CHECK: [[INS1:%[0-9]+]]:_(s128) = G_INSERT [[IMPDEF]], [[LD1]](s64), 0
>> -; CHECK: [[INS2:%[0-9]+]]:_(s128) = G_INSERT [[INS1]], [[LD2]](s64), 64
>> -; CHECK: [[EXT1:%[0-9]+]]:_(s64) = G_EXTRACT [[INS2]](s128), 0
>> -; CHECK: [[EXT2:%[0-9]+]]:_(s64) = G_EXTRACT [[INS2]](s128), 64
>>
>> ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
>> ; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
>> ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]](s64)
>> -; CHECK: G_STORE [[EXT1]](s64), [[ADDR]](p0) :: (store 8 into stack, align 1)
>> +; CHECK: G_STORE [[LD1]](s64), [[ADDR]](p0) :: (store 8 into stack, align 1)
>>
>> ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
>> ; CHECK: [[OFF:%[0-9]+]]:_(s64) = COPY [[CST]]
>> ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
>> -; CHECK: G_STORE [[EXT2]](s64), [[ADDR]](p0) :: (store 8 into stack + 8, align 1)
>> +; CHECK: G_STORE [[LD2]](s64), [[ADDR]](p0) :: (store 8 into stack + 8, align 1)
>> define void @test_split_struct([2 x i64]* %ptr) {
>> %struct = load [2 x i64], [2 x i64]* %ptr
>> call void @take_split_struct([2 x i64]* null, i64 1, i64 2, i64 3,
>>
>> Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll?rev=364512&r1=364511&r2=364512&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll (original)
>> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll Thu Jun 27 02:18:03 2019
>> @@ -112,20 +112,11 @@ define {double, i64, i32} @test_struct_r
>> ; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
>> ; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP %0, [[CST3]](s64)
>> ; CHECK: [[LD4:%[0-9]+]]:_(s64) = G_LOAD [[GEP3]](p0) :: (load 8 from %ir.addr + 24)
>> -; CHECK: [[IMPDEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
>> -; CHECK: [[INS1:%[0-9]+]]:_(s256) = G_INSERT [[IMPDEF]], [[LD1]](s64), 0
>> -; CHECK: [[INS2:%[0-9]+]]:_(s256) = G_INSERT [[INS1]], [[LD2]](s64), 64
>> -; CHECK: [[INS3:%[0-9]+]]:_(s256) = G_INSERT [[INS2]], [[LD3]](s64), 128
>> -; CHECK: [[ARG:%[0-9]+]]:_(s256) = G_INSERT [[INS3]], [[LD4]](s64), 192
>> -; CHECK: [[E0:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 0
>> -; CHECK: [[E1:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 64
>> -; CHECK: [[E2:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 128
>> -; CHECK: [[E3:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 192
>> -
>> -; CHECK: $x0 = COPY [[E0]](s64)
>> -; CHECK: $x1 = COPY [[E1]](s64)
>> -; CHECK: $x2 = COPY [[E2]](s64)
>> -; CHECK: $x3 = COPY [[E3]](s64)
>> +
>> +; CHECK: $x0 = COPY [[LD1]](s64)
>> +; CHECK: $x1 = COPY [[LD2]](s64)
>> +; CHECK: $x2 = COPY [[LD3]](s64)
>> +; CHECK: $x3 = COPY [[LD4]](s64)
>> ; CHECK: BL @arr_callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1, implicit-def $x2, implicit-def $x3
>> ; CHECK: [[E0:%[0-9]+]]:_(s64) = COPY $x0
>> ; CHECK: [[E1:%[0-9]+]]:_(s64) = COPY $x1
>> @@ -262,20 +253,14 @@ define void @take_128bit_struct([2 x i64
>> ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[ADDR]], [[CST]](s64)
>> ; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 8 from %ir.ptr + 8)
>>
>> -; CHECK: [[IMPDEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
>> -; CHECK: [[INS1:%[0-9]+]]:_(s128) = G_INSERT [[IMPDEF]], [[LO]](s64), 0
>> -; CHECK: [[INS2:%[0-9]+]]:_(s128) = G_INSERT [[INS1]], [[HI]](s64), 64
>> -; CHECK: [[EXTLO:%[0-9]+]]:_(s64) = G_EXTRACT [[INS2]](s128), 0
>> -; CHECK: [[EXTHI:%[0-9]+]]:_(s64) = G_EXTRACT [[INS2]](s128), 64
>> -
>> ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
>> ; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
>> ; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST2]](s64)
>> -; CHECK: G_STORE [[EXTLO]](s64), [[GEP2]](p0) :: (store 8 into stack, align 1)
>> +; CHECK: G_STORE [[LO]](s64), [[GEP2]](p0) :: (store 8 into stack, align 1)
>> ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
>> ; CHECK: [[CST3:%[0-9]+]]:_(s64) = COPY [[CST]]
>> ; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST3]](s64)
>> -; CHECK: G_STORE [[EXTHI]](s64), [[GEP3]](p0) :: (store 8 into stack + 8, align 1)
>> +; CHECK: G_STORE [[HI]](s64), [[GEP3]](p0) :: (store 8 into stack + 8, align 1)
>> define void @test_split_struct([2 x i64]* %ptr) {
>> %struct = load [2 x i64], [2 x i64]* %ptr
>> call void @take_split_struct([2 x i64]* null, i64 1, i64 2, i64 3,
>>
>> Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll?rev=364512&r1=364511&r2=364512&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll (original)
>> +++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll Thu Jun 27 02:18:03 2019
>> @@ -202,11 +202,7 @@ define arm_aapcscc [3 x i32] @test_tiny_
>> ; CHECK: liveins: $r0, $r1
>> ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
>> ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
>> -; CHECK: [[IMPDEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
>> -; CHECK: [[INS1:%[0-9]+]]:_(s64) = G_INSERT [[IMPDEF]], [[R0]](s32), 0
>> -; CHECK: [[INS2:%[0-9]+]]:_(s64) = G_INSERT [[INS1]], [[R1]](s32), 32
>> ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
>> -; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS2]](s64)
>> ; CHECK: $r0 = COPY [[R0]]
>> ; CHECK: $r1 = COPY [[R1]]
>> ; ARM: BL @tiny_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
>> @@ -237,15 +233,7 @@ define arm_aapcscc void @test_multiple_i
>> ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
>> ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2
>> ; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY $r3
>> -; CHECK: [[IMPDEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
>> -; CHECK: [[INS1:%[0-9]+]]:_(s64) = G_INSERT [[IMPDEF]], [[R0]](s32), 0
>> -; CHECK: [[INS2:%[0-9]+]]:_(s64) = G_INSERT [[INS1]], [[R1]](s32), 32
>> -; CHECK: [[IMPDEF2:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
>> -; CHECK: [[INS3:%[0-9]+]]:_(s64) = G_INSERT [[IMPDEF2]], [[R2]](s32), 0
>> -; CHECK: [[INS4:%[0-9]+]]:_(s64) = G_INSERT [[INS3]], [[R3]](s32), 32
>> ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
>> -; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS2]](s64)
>> -; CHECK: [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS4]](s64)
>> ; CHECK: $r0 = COPY [[R0]]
>> ; CHECK: $r1 = COPY [[R1]]
>> ; CHECK: $r2 = COPY [[R2]]
>> @@ -278,11 +266,7 @@ define arm_aapcscc void @test_large_int_
>> ; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
>> ; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
>> ; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
>> -; CHECK: [[IMPDEF:%[0-9]+]]:_(s640) = G_IMPLICIT_DEF
>> -; CHECK: [[INS1:%[0-9]+]]:_(s640) = G_INSERT [[IMPDEF]], [[R0]](s32), 0
>> -; CHECK: [[INS:%[0-9]+]]:_(s640) = G_INSERT {{.*}}, [[LAST_STACK_ELEMENT]](s32), 608
>> ; CHECK: ADJCALLSTACKDOWN 64, 0, 14, $noreg, implicit-def $sp, implicit $sp
>> -; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS]](s640)
>> ; CHECK: $r0 = COPY [[R0]]
>> ; CHECK: $r1 = COPY [[R1]]
>> ; CHECK: $r2 = COPY [[R2]]
>> @@ -324,12 +308,7 @@ define arm_aapcscc [2 x float] @test_fp_
>> ; BIG: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_1]](s32), [[ARR1_0]](s32)
>> ; CHECK: [[ARR2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[ARR2_ID]]
>> ; CHECK: [[ARR2:%[0-9]+]]:_(s64) = G_LOAD [[ARR2_FI]]{{.*}}load 8 from %fixed-stack.[[ARR2_ID]]
>> -; CHECK: [[IMPDEF:%[0-9]+]]:_(s192) = G_IMPLICIT_DEF
>> -; CHECK: [[INS1:%[0-9]+]]:_(s192) = G_INSERT [[IMPDEF]], [[ARR0]](s64), 0
>> -; CHECK: [[INS2:%[0-9]+]]:_(s192) = G_INSERT [[INS1]], [[ARR1]](s64), 64
>> -; CHECK: [[INS3:%[0-9]+]]:_(s192) = G_INSERT [[INS2]], [[ARR2]](s64), 128
>> ; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp
>> -; CHECK: [[ARR0:%[0-9]+]]:_(s64), [[ARR1:%[0-9]+]]:_(s64), [[ARR2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[INS3]](s192)
>> ; CHECK: [[ARR0_0:%[0-9]+]]:_(s32), [[ARR0_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR0]](s64)
>> ; LITTLE: $r0 = COPY [[ARR0_0]](s32)
>> ; LITTLE: $r1 = COPY [[ARR0_1]](s32)
>> @@ -382,23 +361,7 @@ define arm_aapcs_vfpcc [4 x float] @test
>> ; CHECK: [[Z2:%[0-9]+]]:_(s64) = G_LOAD [[Z2_FI]]{{.*}}load 8
>> ; CHECK: [[Z3_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z3_ID]]
>> ; CHECK: [[Z3:%[0-9]+]]:_(s64) = G_LOAD [[Z3_FI]]{{.*}}load 8
>> -; CHECK: [[IMPDEF:%[0-9]+]]:_(s192) = G_IMPLICIT_DEF
>> -; CHECK: [[INS1:%[0-9]+]]:_(s192) = G_INSERT [[IMPDEF]], [[X0]](s64), 0
>> -; CHECK: [[INS2:%[0-9]+]]:_(s192) = G_INSERT [[INS1]], [[X1]](s64), 64
>> -; CHECK: [[INS3:%[0-9]+]]:_(s192) = G_INSERT [[INS2]], [[X2]](s64), 128
>> -; CHECK: [[IMPDEF2:%[0-9]+]]:_(s96) = G_IMPLICIT_DEF
>> -; CHECK: [[INS4:%[0-9]+]]:_(s96) = G_INSERT [[IMPDEF2]], [[Y0]](s32), 0
>> -; CHECK: [[INS5:%[0-9]+]]:_(s96) = G_INSERT [[INS4]], [[Y1]](s32), 32
>> -; CHECK: [[INS6:%[0-9]+]]:_(s96) = G_INSERT [[INS5]], [[Y2]](s32), 64
>> -; CHECK: [[IMPDEF3:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
>> -; CHECK: [[INS7:%[0-9]+]]:_(s256) = G_INSERT [[IMPDEF3]], [[Z0]](s64), 0
>> -; CHECK: [[INS8:%[0-9]+]]:_(s256) = G_INSERT [[INS7]], [[Z1]](s64), 64
>> -; CHECK: [[INS9:%[0-9]+]]:_(s256) = G_INSERT [[INS8]], [[Z2]](s64), 128
>> -; CHECK: [[INS10:%[0-9]+]]:_(s256) = G_INSERT [[INS9]], [[Z3]](s64), 192
>> ; CHECK: ADJCALLSTACKDOWN 32, 0, 14, $noreg, implicit-def $sp, implicit $sp
>> -; CHECK: [[X0:%[0-9]+]]:_(s64), [[X1:%[0-9]+]]:_(s64), [[X2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[INS3]](s192)
>> -; CHECK: [[Y0:%[0-9]+]]:_(s32), [[Y1:%[0-9]+]]:_(s32), [[Y2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS6]](s96)
>> -; CHECK: [[Z0:%[0-9]+]]:_(s64), [[Z1:%[0-9]+]]:_(s64), [[Z2:%[0-9]+]]:_(s64), [[Z3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[INS10]](s256)
>> ; CHECK: $d0 = COPY [[X0]](s64)
>> ; CHECK: $d1 = COPY [[X1]](s64)
>> ; CHECK: $d2 = COPY [[X2]](s64)
>> @@ -457,9 +420,7 @@ define arm_aapcscc [2 x i32*] @test_toug
>> ; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
>> ; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
>> ; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
>> -; CHECK: [[INS:%[0-9]+]]:_(s768) = G_INSERT {{.*}}, [[LAST_STACK_ELEMENT]](s32), 736
>> ; CHECK: ADJCALLSTACKDOWN 80, 0, 14, $noreg, implicit-def $sp, implicit $sp
>> -; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS]](s768)
>> ; CHECK: $r0 = COPY [[R0]]
>> ; CHECK: $r1 = COPY [[R1]]
>> ; CHECK: $r2 = COPY [[R2]]
>> @@ -495,11 +456,7 @@ define arm_aapcscc {i32, i32} @test_stru
>> ; CHECK: liveins: $r0, $r1
>> ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
>> ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
>> -; CHECK: [[IMPDEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
>> -; CHECK: [[INS1:%[0-9]+]]:_(s64) = G_INSERT [[IMPDEF]], [[X0]](s32), 0
>> -; CHECK: [[INS2:%[0-9]+]]:_(s64) = G_INSERT [[INS1]], [[X1]](s32), 32
>> ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
>> -; CHECK: [[X0:%[0-9]+]]:_(s32), [[X1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS2]](s64)
>> ; CHECK-DAG: $r0 = COPY [[X0]](s32)
>> ; CHECK-DAG: $r1 = COPY [[X1]](s32)
>> ; ARM: BL @structs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
>>
>>
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