[PATCH] D54409: PowerPC/SPE: Fix load/store handling for SPE

[Kei Thomsen via Phabricator via llvm-commits]

kthomsen added a comment.

I integrated the last patch (yes it is working) and saw, that there can be a another optimization. It is now checking for the Offset to fit into the 8-bit offset of the EVLDD / EVSTD, including an alignment of 8. This reduces the effort if variables are stored on the stack and if the variable is in a range short enough, to be addressed directly.

  --- PPCISelLowering.orig.h      2019-06-28 09:45:05.061923700 +0200
  +++ PPCISelLowering.h   2019-06-28 09:07:19.143760400 +0200
  @@ -1200,6 +1200,9 @@ namespace llvm {
     bool isIntS16Immediate(SDNode *N, int16_t &Imm);
     bool isIntS16Immediate(SDValue Op, int16_t &Imm);
   
  +  bool isIntS8Immediate(SDNode *N, int8_t &Imm);
  +  bool isIntS8Immediate(SDValue Op, int8_t &Imm);
  +
   } // end namespace llvm
   
   #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
  --- PPCISelLowering.orig.cpp    2019-06-28 09:45:47.495524500 +0200
  +++ PPCISelLowering.cpp 2019-06-28 10:07:31.750129100 +0200
  @@ -2227,6 +2227,23 @@ bool llvm::isIntS16Immediate(SDValue Op,
     return isIntS16Immediate(Op.getNode(), Imm);
   }
   
  +/// isIntS8Immediate - This method tests to see if the node is either a 32-bit
  +/// or 64-bit immediate, and if the value can be accurately represented as a
  +/// sign extension from a 8-bit value.  If so, this returns true and the
  +/// immediate.
  +bool llvm::isIntS8Immediate(SDNode *N, int8_t &Imm) {
  +  if (!isa<ConstantSDNode>(N))
  +    return false;
  +  Imm = (int8_t)cast<ConstantSDNode>(N)->getZExtValue();
  +  if (N->getValueType(0) == MVT::i32)
  +    return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
  +  else
  +    return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
  +}
  +bool llvm::isIntS8Immediate(SDValue Op, int8_t &Imm) {
  +  return isIntS8Immediate(Op.getNode(), Imm);
  +}
  +
   /// SelectAddressEVXRegReg - Given the specified address, check to see if it can
   /// be represented as an indexed [r+r] operation.
   bool PPCTargetLowering::SelectAddressEVXRegReg(SDValue N, SDValue &Base,
  @@ -2259,8 +2276,15 @@ bool PPCTargetLowering::SelectAddressReg
       if (hasSPE())
         // Is there any SPE load/store (f64), which can't handle 16bit offset?
         // SPE load/store can only handle 8-bit offsets.
  -      if (SelectAddressEVXRegReg(N, Base, Index, DAG))
  -        return true;
  +      if (SelectAddressEVXRegReg(N, Base, Index, DAG)) {
  +        int8_t imm8 = 0;
  +        // Check if the offset is small enough to fit into the 8-bit
  +        // e.g. a value on the stack
  +        if (isIntS8Immediate(N.getOperand(1), imm8) && !(imm8 % 8))
  +          return false; // offset is okay for the 8-bit offset 
  +        else
  +          return true; // offset is > 8-bit or unknown yet
  +      }
       if (isIntS16Immediate(N.getOperand(1), imm) &&
           (!EncodingAlignment || !(imm % EncodingAlignment)))
         return false; // r+i

What do you think?
Best regards, Kei


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54409/new/

https://reviews.llvm.org/D54409