[PATCH] D63910: [AArch64][GlobalISel] Overhaul legalization & isel or shifts to select immediate forms

[Amara Emerson via Phabricator via llvm-commits]

aemerson created this revision.
aemerson added reviewers: paquette, arsenm.
aemerson added a project: LLVM.
Herald added subscribers: Petar.Avramovic, hiraditya, kristof.beyls, tpr, javed.absar, rovka, nhaehnle, wdng, jvesely.
aemerson added a comment.

I decided to not change the existing AArch64 SelectionDAG patterns to use i32 because there were a few too many places that hard coded it in, in lowering as well as the TableGen.


There are two main issues preventing us from generating immediate form shifts:
a) We have partial SelectionDAG imported support for G_ASHR and G_LSHR shift immediate forms, but they currently don't work because the amount type is expected to be an s64 constant, but we only legalize them to have homogenous types.

To deal with this, first we introduce a custom legalizer to *only* custom legalize s32 shifts which have a constant operand into a s64.

There is also an additional artifact combiner to fold zexts(g_constant) to a larger G_CONSTANT if it's legal, a counterpart to the anyext version committed in an earlier patch.

b) For G_SHL the importer can't cope with the pattern. For this I introduced an early selection phase in the arm64 selector to select these forms manually before the tablegen selector pessimizes it to a register-register variant.

@arsenm A minor change to AMDGPU tests because of the new artifact combiner.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D63910

Files:
  llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
  llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
  llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
  llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
  llvm/lib/Target/AArch64/AArch64LegalizerInfo.h
  llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
  llvm/lib/Target/AArch64/AArch64RegisterBankInfo.h
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
  llvm/test/CodeGen/AArch64/GlobalISel/regbank-shift-imm-64.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir

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