[llvm] r364560 - [ARM] Fix formatting issue in ARMISelLowering.cpp

[Sam Tebbs via llvm-commits]

Author: samtebbs
Date: Thu Jun 27 09:28:28 2019
New Revision: 364560

URL: http://llvm.org/viewvc/llvm-project?rev=364560&view=rev
Log:
[ARM] Fix formatting issue in ARMISelLowering.cpp

Fix a formatting error in ARMISelLowering.cpp::Expand64BitShift. My test
commit after receiving write access.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=364560&r1=364559&r2=364560&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 27 09:28:28 2019
@@ -5565,7 +5565,8 @@ static SDValue Expand64BitShift(SDNode *
     return SDValue();
 
   // If we are in thumb mode, we don't have RRX.
-  if (ST->isThumb1Only()) return SDValue();
+  if (ST->isThumb1Only())
+    return SDValue();
 
   // Okay, we have a 64-bit SRA or SRL of 1.  Lower this to an RRX expr.
   SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),